[coreboot] [flashrom] r568 - trunk
Idwer Vollering
vidwer at gmail.com
Wed Jun 3 18:20:35 CEST 2009
2009/6/3 <svn at coreboot.org>
> Author: libv
> Date: 2009-06-03 09:50:39 +0200 (Wed, 03 Jun 2009)
> New Revision: 568
>
> Modified:
> trunk/board_enable.c
> Log:
> Board enable: Gigabyte GA K8N SLI.
>
> Raises bits 0 and 2 on offset 0xE1 in the system control area of the
> nvidia ck804 lpc.
>
> Signed-off-by: Luc Verhaegen <libv at skynet.be>
> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
> Acked-by: Alexander Gordeev <lasaine at lvk.cs.msu.su>
>
>
> Modified: trunk/board_enable.c
> ===================================================================
> --- trunk/board_enable.c 2009-06-02 19:54:22 UTC (rev 567)
> +++ trunk/board_enable.c 2009-06-03 07:50:39 UTC (rev 568)
> @@ -372,6 +372,31 @@
> return 0;
> }
>
> +/**
> + * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge.
> + */
> +static int board_ga_k8n_sli(const char *name)
> +{
> + struct pci_dev *dev;
> + uint32_t base;
> + uint8_t tmp;
> +
> + dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 LPC */
> + if (!dev) {
> + fprintf(stderr, "\nERROR: NVIDIA LPC bridge not found.\n");
> + return -1;
> + }
> +
> + base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control
> area */
> +
> + /* if anyone knows more about nvidia lpcs, feel free to explain
> this */
> + tmp = inb(base + 0xE1);
> + tmp |= 0x05;
> + outb(tmp, base + 0xE1);
> +
> + return 0;
> +}
> +
> static int board_hp_dl145_g3_enable(const char *name)
> {
> /* Set GPIO lines in the Broadcom HT-1000 southbridge. */
> @@ -670,6 +695,7 @@
> {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0,
> "epox", "ep-bx3", "EPoX", "EP-BX3",
> board_epox_ep_bx3},
> {0x1039, 0x0761, 0, 0, 0, 0, 0, 0,
> "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK",
> it87xx_probe_spi_flash},
> {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000,
> NULL, NULL, "GIGABYTE", "GA-7VT600",
> board_biostar_p4m80_m4},
> + {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000,
> NULL, NULL, "GIGABYTE", "GA-K8N-SLI",
> board_ga_k8n_sli},
> {0x10de, 0x0360, 0, 0, 0, 0, 0, 0,
> "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4",
> it87xx_probe_spi_flash},
> {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0,
> "gigabyte", "m61p", "GIGABYTE", "GA-M61P-S3",
> it87xx_probe_spi_flash},
> {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000,
> NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H",
> it87xx_probe_spi_flash},
> @@ -787,7 +813,6 @@
> { "Boser", "HS-6637", },
> { "DFI", "855GME-MGF", },
> { "FIC", "VA-502", },
> - { "GIGABYTE", "GA-K8N-SLI", },
> { "MSI", "MS-6178", },
> { "MSI", "MS-7260 (K9N Neo)", },
> { "PCCHIPS", "M537DMA33", },
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
Make FreeBSD's gmake happy.
Signed-off-by: Idwer Vollering <vidwer at gmail.com>
Index: board_enable.c
===================================================================
--- board_enable.c (revision 568)
+++ board_enable.c (working copy)
@@ -390,9 +390,9 @@
base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area
*/
/* if anyone knows more about nvidia lpcs, feel free to explain this
*/
- tmp = inb(base + 0xE1);
+ tmp = INB(base + 0xE1);
tmp |= 0x05;
- outb(tmp, base + 0xE1);
+ OUTB(tmp, base + 0xE1);
return 0;
}
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20090603/2fc7ebd0/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: flashrom_fbsd_fix_r568.diff
Type: text/x-patch
Size: 464 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20090603/2fc7ebd0/attachment.diff>
More information about the coreboot
mailing list