[coreboot] write/verify bug
Richard Smith
smithbone at gmail.com
Fri Jun 12 18:42:53 CEST 2009
Carl-Daniel Hailfinger wrote:
>>
>> On the 8Mbit OLPC part with 256 byte pages that 4096 pages. So 4
>> about seconds for each additional USB transaction.
>
> The idea is to check if the erase worked after each erase operation.
> Basically, if you have an eraseblock size of 64 kByte, there should be
> exactly one 64 kByte read after erasing. I have not yet seen SPI chips
> with 256 Byte eraseblock size, but if you did, please tell me the part
> number so I can take a look at the data sheet.
Right. I wasn't talking about erase. Just verifying after each page
write vs writing the entire image and then re-reading the part in one
stream read.
While on the subject of erase though. I find thats its much nicer to
use block erase rather than full chip erase although perhaps a bit slower.
The (very OLPC specific) advantage is that if I just update the EC code
then only the 1st 64k block is erased/written.
The OLPC firmware reflash also does things in a block erase fashion so
that if things go wrong (power loss) there's the highest chance of a
system that might still boot.
If you chip erase and you have some sort of bad power event half-way you
are dead since your reset vector is all 0xff but the system that does it
a sector at a time would probably still boot enough to allow you to reflash.
--
Richard A. Smith
smithbone at gmail.com
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