[coreboot] EP80579 Mainboard support
joe at settoplinux.org
Wed Jun 24 17:02:18 CEST 2009
On Wed, 24 Jun 2009 07:29:02 -0700, Ed Swierk <eswierk at aristanetworks.com>
> On Wed, Jun 24, 2009 at 6:36 AM, Arnaud Maye<arnaud.maye at 4dsp.com> wrote:
>> I've tried a reverse engineer approach. Plug a DIMM into the system and
>> launch Linux with the
>> legacy BIOS. lspci -xxx then shows me the IMCH BAR and implicitly the
>> settings doctored by the
>> legacy BIOS. The first try I've done was to try the r-e DRT0/DRT1 in the
>> coreboot RAM init code.
>> Not much differences so far. But anyway I've seen quite a lot of
>> around the ODT register
>> and such. So there is still some hope.
> Have you tried 2T timing? This causes the memory controller to wait an
> extra cycle before sending a command. The delay can compensate for
> slight misconfiguration of other signal timing settings so it's a good
> place to start.
> Also try different RCOMP values. I have no idea what RCOMP is but I
> remember having to tweak it to get the memory to behave.
FYI, RCOMP (resistive compensation) is part of the Buffer Strength
calculation. I far as I know there are no public docs explaining RCOMP but
(hint:-)) there may possibly be patents that explain it.
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