[coreboot] Integrate the kernel into 49LF004...
Uwe Hermann
uwe at hermann-uwe.de
Fri Jun 26 20:50:17 CEST 2009
On Thu, Jun 25, 2009 at 08:23:42PM -0700, Rick Ant wrote:
> Thanks for the info here's the info of my machine :
> Step 1...
> Board vendor : unknown
> Processor : Intel Pentium III
> Northbridge : Intel 82810
> Southbridge : Intel 82801 AA
> BIOS Chip : SST 49LF004
> Network Chip : RTL 8100C
> Memory Bank : 1 Bank DDR SDRAM, I put on 128 Mbyte
>
> Step 2 :
> lspci -tvnn result:
> -[00]-+-00.0 8086:7120
> +-01.0 8086:7121
> +-1e.0-[01]----0a.0 10ec:8139
> +-1f.0 8086:2410
> +-1f.1 8086:2411
> +-1f.2 8086:2412
> +-1f.3 8086:2413
> \-1f.5 8086:2415
>
> Step 3 :
> Super I/O chip on this board : Winbond W83627 HG - AW
> Step 4 :
> BIOS Device : SST 49LF004B 512 Kbytes EEPROM
First, please tell us the vendor and name of your mainboard.
Then, please post the following information, I may be able to give you
a first coreboot patch for your board which you can test on real hardware.
Make sure you have a working known-good backup chip and a null-modem
cable for debug output before trying any of this on real hardware,
though.
We'll need:
- "lspci" output (the 'lspci -tvnn' above doesn't show device names strangely).
- "superiotool -deV" output.
- "./getpir" output (a file called irq_table.c).
This tool is in a v2 checkout in util/getpir.
- "./mptable" output.
This tool is in a v2 checkout in util/mptable.
- "flashrom -V" output.
(http://www.coreboot.org/Flashrom)
Please join #coreboot on IRC for real-time help and debugging if you
have problems with or questions about the above stuff.
Uwe.
--
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