[coreboot] [v2] r4375 - trunk/util/superiotool

svn at coreboot.org svn at coreboot.org
Sat Jun 27 04:23:27 CEST 2009


Author: uwe
Date: 2009-06-27 04:23:26 +0200 (Sat, 27 Jun 2009)
New Revision: 4375

Modified:
   trunk/util/superiotool/smsc.c
Log:
Add dump support for SMSC LPC47N252.

Signed-off-by: Fran?\195?\167ois-Regis Vuillemin <coreboot at miradou.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/util/superiotool/smsc.c
===================================================================
--- trunk/util/superiotool/smsc.c	2009-06-26 15:53:07 UTC (rev 4374)
+++ trunk/util/superiotool/smsc.c	2009-06-27 02:23:26 UTC (rev 4375)
@@ -109,6 +109,45 @@
 			{0x00,0x00,0x00,EOT}},
 		{EOT}}},
 	{0x0e, "LPC47N252", {	/* From sensors-detect */
+		{NOLDN, NULL,
+			{0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,
+			 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT},
+			{0x0e,NANA,0x00,0x00,0x04,0x04,NANA,NANA,0x00,
+			 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}},
+		{0x0, "Floppy",
+			{0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf3,0xf4,
+			 0xf5,EOT},
+			{0x00,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,RSVD,0x00,
+			 0x00,EOT}},
+		{0x1, "Power management (PM1)",
+			{0x30,0x60,0x61,EOT},
+			{0x00,0x00,0x00,EOT}},
+		{0x3, "Parallel port",
+			{0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT},
+			{0x00,0x00,0x00,0x00,0x04,0x3c,0x00,EOT}},
+		{0x4, "COM1",
+			{0x30,0x60,0x61,0x70,0xf0,EOT},
+			{0x00,0x00,0x00,0x00,0x00,EOT}},
+		{0x5, "COM2 / IRCC",
+			{0x30,0x60,0x61,0x62,0x63,0x70,0x74,0xf0,0xf1,
+			 0xf2,0xf7,0xf8,EOT},
+			{0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x02,
+			 0x03,0x00,0x00,EOT}},
+		{0x6, "Real-time clock (RTC)",
+			{0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,EOT},
+			{0x00,0x00,0x70,0x00,0x74,0x00,0x00,NANA,EOT}},
+		{0x7, "Keyboard",
+			{0x30,0x60,0x61,0x70,0x72,0xf0,EOT},
+			{0x00,0x00,0x00,0x00,0x00,0x00,EOT}},
+		{0x8, "Embedded controller (EC)",
+			{0x30,0x60,0x61,EOT},
+			{0x00,0x00,0x62,EOT}},
+		{0x9, "Mailbox Interface",
+			{0x30,0x60,0x61,EOT},
+			{0x00,0x00,0x00,EOT}},
+		{0xa, "LPC/8051 addressable GPIO (LGPIO)",
+			{0x30,0x60,0x61,EOT},
+			{0x00,0x00,0x00,EOT}},
 		{EOT}}},
 	{0x14, "LPC47M172", {
 		{EOT}}},





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