[coreboot] [PATCH] v2: fix PCIe/MMCONF config space access
stepan at coresystems.de
Fri Mar 6 19:45:57 CET 2009
On 06.03.2009 19:20 Uhr, Myles Watson wrote:
> It seems like these two snippets should be related in some way. Do
> you have to set them equal?
Yes, the two are related. They're not yet unified - there will be more
patches coming to clean things up, but I need to get my patch queue
smaller in order to not drift away from the public tree.
> Index: src/config/Options.lb
> --- src/config/Options.lb (.../branches/upstream/coreboot-v2)
> +++ src/config/Options.lb (.../trunk/coreboot-v2)
> @@ -983,6 +983,13 @@
> comment "enable mmconfig for pci conf"
> +define MMCONF_BASE_ADDRESS
> + default none
> + format "0x%x"
> + export used
> + comment "enable mmconfig base address"
> from /src/northbridge/intel/i945/northbridge.c:
> /* We use 0xcf as an unused index for our PCIe bar so that we find it again */
> resource = new_resource(dev, 0xcf);
> resource->base = DEFAULT_PCIEXBAR;
> resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */
> resource->flags =
> IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
> printk_debug("Adding PCIe enhanced config space BAR 0x%08x-0x%08x.\n",
> resource->base, (resource->base + resource->size));
> I didn't see anywhere that you enabled the PCI decode space in the
> fam10 code. Is it fixed? How does resource allocation avoid it?
I didn't touch any of the fam10 code, except the obvious MMCONF ->
MMCONF_DEFAULT, because that's what the the code that is there really is
supposed to do.
Hopefully someone can jump in on fam10 and help getting that part
straight. At the moment, I'm focussed on getting it right for the Intel
code and try to fix up some of the AMD parts as far as I can be sure not
to break anything there or make it worse.
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