[coreboot] r4010 - in trunk/coreboot-v2/src/mainboard/amd: dbm690t/acpi pistachio/acpi

[svn at coreboot.org]

Author: hailfinger
Date: 2009-03-17 02:47:25 +0100 (Tue, 17 Mar 2009)
New Revision: 4010

Modified:
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/dsdt.asl
   trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/dsdt.asl
Log:
- TOM2 is filled in by the dynamic ACPI code. Don't hardcode it in the
  DSDT and use the dynamic TOM2 variable instead.
- The DSDT needs to be revision 2 or above to handle 64 bit variables.
  This will require a recent (not older than 2007) iasl (ACPI compiler).
- Fix an incorrect comment.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/dsdt.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/dsdt.asl	2009-03-16 17:28:07 UTC (rev 4009)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi/dsdt.asl	2009-03-17 01:47:25 UTC (rev 4010)
@@ -21,7 +21,7 @@
 DefinitionBlock (
 	"DSDT.AML",           /* Output filename */
 	"DSDT",                 /* Signature */
-	0x01,               	 /* DSDT Revision */
+	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
 	"AMD   ",               /* OEMID */
 	"DBM690T ",          /* TABLE ID */
 	0x00010001	/* OEM Revision */
@@ -32,7 +32,6 @@
 	/* Data to be patched by the BIOS during POST */
 	/* FIXME the patching is not done yet! */
 	/* Memory related values */
-	Name(TOM2, 0x0)	/* Top of RAM memory above 4GB (>> 16) */
 	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
 	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
 	Name(PBLN, 0x0)	/* Length of BIOS area */
@@ -1130,6 +1129,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
+			External (TOM2)
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1476,7 +1476,7 @@
 					0x0000,			/* range minimum */
 					0x0CF7,			/* range maximum */
 					0x0000,			/* translation */
-					0x0CF8			/* Resource source index */
+					0x0CF8			/* length */
 				)
 
 				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,

Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/dsdt.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/dsdt.asl	2009-03-16 17:28:07 UTC (rev 4009)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi/dsdt.asl	2009-03-17 01:47:25 UTC (rev 4010)
@@ -21,7 +21,7 @@
 DefinitionBlock (
 	"DSDT.AML",           /* Output filename */
 	"DSDT",                 /* Signature */
-	0x01,               	 /* DSDT Revision */
+	0x02,        /* DSDT Revision, needs to be 2 for 64bit */
 	"AMD   ",               /* OEMID */
 	"PISTACHI",          /* TABLE ID */
 	0x00010001	/* OEM Revision */
@@ -32,7 +32,6 @@
 	/* Data to be patched by the BIOS during POST */
 	/* FIXME the patching is not done yet! */
 	/* Memory related values */
-	Name(TOM2, 0x0)	/* Top of RAM memory above 4GB (>> 16) */
 	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
 	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
 	Name(PBLN, 0x0)	/* Length of BIOS area */
@@ -1129,6 +1128,7 @@
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
 			External (TOM1)
+			External (TOM2)
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1399,7 +1399,7 @@
 					0x0000,			/* range minimum */
 					0x0CF7,			/* range maximum */
 					0x0000,			/* translation */
-					0x0CF8			/* Resource source index */
+					0x0CF8			/* length */
 				)
 
 				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,