[coreboot] DL145G3

[Stefan Reinauer]

On 27.03.2009 13:11 Uhr, Mondrian Nuessle wrote:
> Hi,
>
> as someone already pointed out, we need to enable flashing first on the board using a GPIO pin.
> I have attached a patch for flashrom that enables flashing on the HP DL145 G3. I tested it on the DL145 I have here.
>
> Please specify the board on the commandline, like in
> # ./flashrom -m "hp:dl145_g3" -E
>
> The patch is probably not ready for primetime, maybe someone can review it?
>
> Regards, Mondrian
>   
> +static int board_hp_dl145_g3_enable(const char *name)
> +{
> +	uint8_t b;
> +   
> +	outb(0x44, 0x0cd6);    
> +	b = inb(0x0cd7) | 0x24;
> +	outb(b, 0x0cd7);
>   

Any chance to find out what hardware is listening at 0xcd6/0xcd7?

Is that covered by PMBASE or GPIOBASE of the southbridge, or the SuperIO?

Stefan

-- 
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: info at coresystems.de  • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866