[coreboot] 945GME + L7400 + 1Gb SODIMM reset problem

Stefan Reinauer stepan at coresystems.de
Tue Mar 31 15:24:55 CEST 2009


Hi, Vadim,

nice to see that you guys are finally looking into coreboot on i945.
It's been a while!
The version you are using requires 2 equal DIMMs populated on the mainboard.

Best wishes,
Stefan



On 31.03.2009 15:31 Uhr, Vadim wrote:
>
> coreboot-3.0.1161 Wed Mar 25 11:26:19 EDT 2009 starting...
> (console_loglevel=8)
>
> Choosing fallback boot.
>
> LAR: Attempting to open 'fallback/initram/segment0'.
>
> LAR: Start 0xfff80000 len 0x80000
>
> LAR: seen member normal/option_table at 0xfff80000, size 984
>
> LAR: seen member normal/initram/segment0 at 0xfff80430, size 21284
>
> LAR: seen member normal/stage2/segment0 at 0xfff857b0, size 1
>
> LAR: seen member normal/stage2/segment1 at 0xfff85810, size 25731
>
> LAR: seen member normal/stage2/segment2 at 0xfff8bcf0, size 999
>
> LAR: seen member normal/payload/segment0 at 0xfff8c130, size 1
>
> LAR: seen member normal/payload/segment1 at 0xfff8c190, size 40402
>
> LAR: seen member normal/payload/segment2 at 0xfff95fc0, size 47
>
> LAR: seen member bootblock at 0xffffafc0, size 20480
>
> LAR: File not found!
>
> LAR: Run file fallback/initram/segment0 failed: No such file.
>
> Fallback failed. Try normal boot
>
> LAR: Attempting to open 'normal/initram/segment0'.
>
> LAR: Start 0xfff80000 len 0x80000
>
> LAR: seen member normal/option_table at 0xfff80000, size 984
>
> LAR: seen member normal/initram/segment0 at 0xfff80430, size 21284
>
> LAR: CHECK normal/initram/segment0 @ 0xfff80430
>
> start 0xfff80480 len 21284 reallen 21284 compression 0 entry
> 0x0000391f loadaddress 0x00000000
>
> Entry point is 0xfff83d9f
>
> Hi there from stage1, cpu0, core0
>
> Mobile Intel(R) 945GM/GME Express Chipset
>
> (G)MCH capable of up to FSB 800 MHz
>
> (G)MCH capable of up to DDR2-667
>
> Setting up static southbridge registers... GPIOS... done.
>
> Disabling Watchdog reboot... done.
>
> Setting up static northbridge registers... done.
>
> Waiting for MCHBAR to come up...ok
>
> SMBus controller enabled.
>
> Setting up RAM controller.
>
> SDRAM_CAPABILITIES_DUAL_CHENAL = 0x00000000
>
> This mainboard supports only Single Channel Operation.
>
> SDRAM_CAPABILITIES_DUAL_CHENAL = 0x00000000
>
> DDR II Channel 0 Socket 0: x8DDS
>
> SDRAM_CAPABILITIES_DUAL_CHENAL = 0x00000000
>
> lowest common cas = 3
>
> Probing Speed 2
>
> DIMM: 0
>
> Current CAS mask: 0038; idx=2, tCLK=50, tAC=60: Not fast enough!
>
> Current CAS mask: 0030; idx=1, tCLK=3d, tAC=50: Not fast enough!
>
> Current CAS mask: 0020; idx=0, tCLK=30, tAC=45: OK
>
> DIMM: 1
>
> freq_cas_mask for speed 2: 0020
>
> Memory will be driven at 667MHz with CAS=5 clocks
>
> tRAS = 15 cycles
>
> tRP = 5 cycles
>
> tRCD = 5 cycles
>
> Refresh: 7.8us
>
> tWR = 5 cycles
>
> DIMM 0 side 0 = 512 MB
>
> DIMM 0 side 1 = 512 MB
>
> tRFC = 35 cycles
>
> Setting Graphics Frequency...
>
> Setting Memory Frequency... CLKCFG=0x00010023, CLKCFG=0x00010043, ok
>
> Setting mode of operation for memory
> channels...SDRAM_CAPABILITIES_DUAL_CHENAL = 0x00000000
>
> Single Channel 0 only.
>
> DCC=0x00000400
>
> Programming Clock Crossing...MEM=667 FSB=667... ok
>
> Setting RAM size...
>
> C0DRB = 0x00002010
>
> C1DRB = 0x00000000
>
> TOLUD = 0x70
>
> Setting row attributes...
>
> C0DRA = 0x0033
>
> C1DRA = 0x0000
>
> one dimm per channel config..
>
> Initializing System Memory IO...
>
> SDRAM_CAPABILITIES_DUAL_CHENAL = 0x00000000
>
> SDRAM_CAPABILITIES_DUAL_CHENAL = 0x00000000
>
> Programming Single Channel RCOMP
>
> Table Index: 19
>
> Programming DLL Timings...
>
> Enabling System Memory IO...
>
> jedec enable sequence: bank 0
>
> Apply NOP
>
> Sending RAM command 0x00010400...done
>
> ram read: 00000000
>
> All Banks Precharge
>
> Sending RAM command 0x00020400...done
>
> ram read: 00000000
>
> Extended Mode Register Set(2)
>
> Sending RAM command 0x00240400...done
>
> ram read: 00000000
>
> Extended Mode Register Set(3)
>
> Sending RAM command 0x00440400...done
>
> ram read: 00000000
>
> Extended Mode Register Set
>
> Sending RAM command 0x00040400...done
>
> SDRAM_CAPABILITIES_DUAL_CHENAL = 0x00000000
>
> ram read: 00000020
>
> MRS: Reset DLLs
>
> Sending RAM command 0x00030400...done
>
> ram read: 00004a98
>
> All Banks Precharge
>
> Sending RAM command 0x00020400...done
>
> ram read: 00000000
>
> CAS before RAS
>
> Sending RAM command 0x00060400...done
>
> ram read: 00000000
>
> ram read: 00000000
>
> MRS: Enable DLLs
>
> Sending RAM command 0x00030400...done
>
> ram read: 00004298
>
> Extended Mode Register Set: ODT/OCD
>
> Sending RAM command 0x00040400...done
>
> SDRAM_CAPABILITIES_DUAL_CHENAL = 0x00000000
>
> ram read: 00001c20
>
> Extended Mode Register Set: OCD Exit
>
> Sending RAM command 0x00040400...done
>
> SDRAM_CAPABILITIES_DUAL_CHENAL = 0x00000000
>
> ram read: 00000020
>
> jedec enable sequence: bank 1
>
> bankaddr from bank size of rank 0
>
> Apply NOP
>
> Sending RAM command 0x00010400...done
>
> ram read: 20000000
>
> All Banks Precharge
>
> Sending RAM command 0x00020400...done
>
> ram read: 20000000
>
> Extended Mode Register Set(2)
>
> Sending RAM command 0x00240400...done
>
> ram read: 20000000
>
> Extended Mode Register Set(3)
>
> Sending RAM command 0x00440400...done
>
> ram read: 20000000
>
> Extended Mode Register Set
>
> Sending RAM command 0x00040400...done
>
> SDRAM_CAPABILITIES_DUAL_CHENAL = 0x00000000
>
> ram read: 20000020
>
> MRS: Reset DLLs
>
> Sending RAM command 0x00030400...done
>
> ram read: 20004a98
>
> All Banks Precharge
>
> Sending RAM command 0x00020400...done
>
> ram read: 20000000
>
> CAS before RAS
>
> Sending RAM command 0x00060400...done
>
> ram read: 20000000
>
> ram read: 20000000
>
> MRS: Enable DLLs
>
> Sending RAM command 0x00030400...done
>
> ram read: 20004298
>
> Extended Mode Register Set: ODT/OCD
>
> Sending RAM command 0x00040400...done
>
> SDRAM_CAPABILITIES_DUAL_CHENAL = 0x00000000
>
> ram read: 20001c20
>
> Extended Mode Register Set: OCD Exit
>
> Sending RAM command 0x00040400...done
>
> SDRAM_CAPABILITIES_DUAL_CHENAL = 0x00000000
>
> ram read: 20000020
>
> jedec enable sequence: bank 4
>
> bankaddr from bank size of rank 1
>
> Apply NOP
>
> Sending RAM command 0x00010400...done
>
> ram read: 40000000
>
> All Banks Precharge
>
> Sending RAM command 0x00020400...done
>
> ram read: 40000000
>
> Extended Mode Register Set(2)
>
> Sending RAM command 0x00240400...done
>
> ram read: 40000000
>
> Extended Mode Register Set(3)
>
> Sending RAM command 0x00440400...done
>
> ram read: 40000000
>
> Extended Mode Register Set
>
> Sending RAM command 0x00040400...done
>
> SDRAM_CAPABILITIES_DUAL_CHENAL = 0x00000000
>
> ram read: 40000020
>
> MRS: Reset DLLs
>
> Sending RAM command 0x00030400...done
>
> ram read: 40004a98
>
> All Banks Precharge
>
> Sending RAM command 0x00020400...done
>
> ram read: 40000000
>
> CAS before RAS
>
> Sending RAM command 0x00060400...done
>
> ram read: 40000000
>
> ram read: 40000000
>
> MRS: Enable DLLs
>
> Sending RAM command 0x00030400...done
>
> ram read: 40004298
>
> Extended Mode Register Set: ODT/OCD
>
> Sending RAM command 0x00040400...done
>
> SDRAM_CAPABILITIES_DUAL_CHENAL = 0x00000000
>
> ram read: 40001c20
>
> Extended Mode Register Set: OCD Exit
>
> Sending RAM command 0x00040400...done
>
> SDRAM_CAPABILITIES_DUAL_CHENAL = 0x00000000
>
> ram read: 40000020
>
> Normal Operation
>
> Sending RAM command 0x000f0400...done
>
> receive_enable_autoconfig() for channel 0
>
> find_strobes_low()
>
> set_receive_enable() medium=0x3, coarse=0x5
>
> set_receive_enable() medium=0x1, coarse=0x5
>
> find_strobes_edge()
>
> set_receive_enable() medium=0x1, coarse=0x5
>
> add_quarter_clock() mediumcoarse=15 fine=d7
>
> set_receive_enable() medium=0x3, coarse=0x5
>
> find_preamble()
>
> set_receive_enable() medium=0x3, coarse=0x4
>
> set_receive_enable() medium=0x3, coarse=0x3
>
> add_quarter_clock() mediumcoarse=0f fine=57
>
> normalize()
>
> RAM initialization finished.
>
> Setting up Egress Port RCRB
>
> Loading port arbitration table ...ok
>
> Wait for VC1 negotiation ...ok
>
> Setting up DMI RCRB
>
> Wait for VC1 negotiation ...timeout!
>
> Waiting for DMI hardware...ok
>
> Disabling PCI Express x16 Link
>
> Wait for link to enter detect state... ok
>
> Setting up Root Complex Topology
>
> run_file returns with 0
>
> Done RAM init code
>
> Done printk() buffer move
>
> disable_car entry
>
> disable_car global_vars copy done
>
> NEWLOCATION = 0x00088fc8
>
> disable_car global_vars pointer adjusted
>
> entering asm code now
>
> LAR: Attempting to open 'normal/stage2/segment0'.
>
> LAR: Start 0xfff80000 len 0x80000
>
> LAR: seen member normal/option_table at 0xfff80000, size 984
>
> LAR: seen member normal/initram/segment0 at 0xfff80430, size 21284
>
> LAR: seen member normal/stage2/segment0 at 0xfff857b0, size 1
>
> LAR: CHECK normal/stage2/segment0 @ 0xfff857b0
>
> start 0xfff85800 len 1 reallen 194976 compression 3 entry 0x00002048
> loadaddress 0x00016780
>
> LAR: Compression algorithm #3 (zeroes) used
>
> LAR: Attempting to open 'normal/stage2/segment1'.
>
> LAR: Start 0xfff80000 len 0x80000
>
> LAR: seen member normal/option_table at 0xfff80000, size 984
>
> LAR: seen member normal/initram/segment0 at 0xfff80430, size 21284
>
> LAR: seen member normal/stage2/segment0 at 0xfff857b0, size 1
>
> LAR: seen member normal/stage2/segment1 at 0xfff85810, size 25731
>
> LAR: CHECK normal/stage2/segment1 @ 0xfff85810
>
> start 0xfff85860 len 25731 reallen 53312 compression 1 entry
> 0x00002048 loadaddress 0x00002000
>
> LAR: Compression algorithm #1 (lzma) used
>
> LAR: Attempting to open 'normal/stage2/segment2'.
>
> LAR: Start 0xfff80000 len 0x80000
>
> LAR: seen member normal/option_table at 0xfff80000, size 984
>
> LAR: seen member normal/initram/segment0 at 0xfff80430, size 21284
>
> LAR: seen member normal/stage2/segment0 at 0xfff857b0, size 1
>
> LAR: seen member normal/stage2/segment1 at 0xfff85810, size 25731
>
> LAR: seen member normal/stage2/segment2 at 0xfff8bcf0, size 999
>
> LAR: CHECK normal/stage2/segment2 @ 0xfff8bcf0
>
> start 0xfff8bd40 len 999 reallen 26420 compression 1 entry 0x00002048
> loadaddress 0x00010040
>
> LAR: Compression algorithm #1 (lzma) used
>
> LAR: Attempting to open 'normal/stage2/segment3'.
>
> LAR: Start 0xfff80000 len 0x80000
>
> LAR: seen member normal/option_table at 0xfff80000, size 984
>
> LAR: seen member normal/initram/segment0 at 0xfff80430, size 21284
>
> LAR: seen member normal/stage2/segment0 at 0xfff857b0, size 1
>
> LAR: seen member normal/stage2/segment1 at 0xfff85810, size 25731
>
> LAR: seen member normal/stage2/segment2 at 0xfff8bcf0, size 999
>
> LAR: seen member normal/payload/segment0 at 0xfff8c130, size 1
>
> LAR: seen member normal/payload/segment1 at 0xfff8c190, size 40402
>
> LAR: seen member normal/payload/segment2 at 0xfff95fc0, size 47
>
> LAR: seen member bootblock at 0xffffafc0, size 20480
>
> LAR: File not found!
>
> LAR: load_file: No such file 'normal/stage2/segment3'
>
> LAR: load_file_segments: All loaded, entry 0x00002048
>
> resets at this point .
>
> Best Regards,
>
> Vadim
>
>  
>
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