[coreboot] cbfs XIP patch
rminnich at gmail.com
Tue May 5 19:59:40 CEST 2009
On Tue, May 5, 2009 at 10:50 AM, Peter Stuge <peter at stuge.se> wrote:
> No sir.
This is great!
> None have single byte erase blocks, but most of the SPI flash chips
> can actually do 256 byte erase blocks.
Should we move to 256 byte default alignment?
> I keep imagining how I will be able to safely update the coreboot
> normal image but keep fallback, stages and payloads untouched.
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