[coreboot] cbfs XIP patch

[Peter Stuge]

Myles Watson wrote:
> > None have single byte erase blocks, but most of the SPI flash chips
> > can actually do 256 byte erase blocks.
> 
> Since erase block granularity is chip dependent, shouldn't flashrom
> be in charge of touching the minimal number of blocks?  I don't see
> how CBFS can know which chip it will be used in.

Correct, it can't on it's own, and I think flash writing and cbfs
expertise will go together eventually. I expect cbfstool and flashrom
to converge a bit. Not all the way into one tool, but they will be
close.


> What's the most common boundary?  1K, 2K, 4K?  Should we pick one
> that is reasonable?

Fun fun. A few chips even have odd-byte boundaries like 4300 bytes or
whatever. And some are very much not symmetrical.

I think it's impossible to pick a good universal default. The target
flash chip layout is required information. I expect the final
decision to be defered until actual flash write time. It could
certainly be the case that not everything in the flash chip can be
aligned into it's own block at that point.


//Peter