[coreboot] Board enable for Epox 8K5A2.

Luc Verhaegen libv at skynet.be
Thu May 7 19:14:03 CEST 2009


I didn't prepend this with [PATCH] yet, as i still need to verify this 
change on an epia-m with its original bios...

This patch adds support for the Epox 8k5a2 motherboard as owned by Kevin 
Sopp (CC). His lspci is attached for future reference. Kevin still needs 
to try this code too. His board is properly matched by pci subsystem 
ids, as there is one proper epox id in there, and the other id was 
copied from the device id (which is already better than leaving it 
blank).

This motherboard requires just the MEMW# on the winbond superio to be 
raised for it to work. 2 more boards with vt823x need this as well.

There are two other functions needed by other vt823x based boards;
* raising a vt823x gpio line (used 2x).
* enabling memory writes to always hit lpc on vt823x (used 2x).

By putting this code into separate functions, the vt823x board enables 
become very simple, with only the msi on still needing to poke a single 
pci bit on its own.

Luc Verhaegen.
-------------- next part --------------
Index: board_enable.c
===================================================================
--- board_enable.c	(revision 472)
+++ board_enable.c	(working copy)
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 2005-2007 coresystems GmbH <stepan at coresystems.de>
  * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
- * Copyright (C) 2007-2008 Luc Verhaegen <libv at skynet.be>
+ * Copyright (C) 2007-2009 Luc Verhaegen <libv at skynet.be>
  * Copyright (C) 2007 Carl-Daniel Hailfinger
  *
  * This program is free software; you can redistribute it and/or modify
@@ -152,6 +152,65 @@
 }
 
 /**
+ * w83627: Enable MEMW# and set ROM size to max.
+ */
+static void w8326xx_memw_enable(uint16_t index)
+{
+	w836xx_ext_enter(index);
+	if (!(wbsio_read(index, 0x24) & 0x02)) {	/* Flash ROM enabled? */
+		/* Enable MEMW# and set ROM size select to max. (4M). */
+		wbsio_mask(0x2e, 0x24, 0x28, 0x28);
+	}
+	w836xx_ext_leave(index);
+}
+
+/**
+ * Common routine for several VT823x based boards.
+ */
+static void vt823x_set_all_writes_to_lpc(struct pci_dev *dev)
+{
+	uint8_t val;
+
+	/* All memory cycles, not just ROM ones, go to LPC */
+	val = pci_read_byte(dev, 0x59);
+	val &= ~0x80;
+	pci_write_byte(dev, 0x59, val);
+}
+
+/**
+ * VT823x: Set one of the GPIO pins.
+ */
+static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise)
+{
+	uint16_t base;
+	uint8_t val, bit;
+
+	if ((gpio < 12) || (gpio > 15)) {
+		fprintf(stderr, "\nERROR: "
+			"VT8235 GPIO%02d is not implemented.\n", gpio);
+		return;
+	}
+
+	/* GPIO12-15 -> output */
+	val = pci_read_byte(dev, 0xE4);
+	val |= 0x10;
+	pci_write_byte(dev, 0xE4, val);
+
+	/* now raise/drop the gpio line itself */
+	bit = 0x01 << (gpio >> 7);
+
+	/* We need the I/O Base Address for this board's flash enable. */
+	base = pci_read_word(dev, 0x88) & 0xff80;
+
+	val = INB(base + 0x4D);
+	if (raise)
+		val |= bit;
+	else
+		val &= ~bit;
+	OUTB(val, base + 0x4D);
+}
+
+/**
  * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
  *
  * We don't need to do this when using coreboot, GPIO15 is never lowered there.
@@ -159,8 +218,6 @@
 static int board_via_epia_m(const char *name)
 {
 	struct pci_dev *dev;
-	uint16_t base;
-	uint8_t val;
 
 	dev = pci_dev_find(0x1106, 0x3177);	/* VT8235 ISA bridge */
 	if (!dev) {
@@ -168,19 +225,9 @@
 		return -1;
 	}
 
-	/* GPIO12-15 -> output */
-	val = pci_read_byte(dev, 0xE4);
-	val |= 0x10;
-	pci_write_byte(dev, 0xE4, val);
+	/* GPIO15 is connected to write protect. */
+	vt823x_gpio_set(dev, 15, 1);
 
-	/* Get Power Management IO address. */
-	base = pci_read_word(dev, 0x88) & 0xFF80;
-
-	/* Enable GPIO15 which is connected to write protect. */
-	val = INB(base + 0x4D);
-	val |= 0x80;
-	OUTB(val, base + 0x4D);
-
 	return 0;
 }
 
@@ -192,7 +239,6 @@
 static int board_asus_a7v8x_mx(const char *name)
 {
 	struct pci_dev *dev;
-	uint8_t val;
 
 	dev = pci_dev_find(0x1106, 0x3177);	/* VT8235 ISA bridge */
 	if (!dev)
@@ -202,29 +248,18 @@
 		return -1;
 	}
 
-	/* This bit is marked reserved actually. */
-	val = pci_read_byte(dev, 0x59);
-	val &= 0x7F;
-	pci_write_byte(dev, 0x59, val);
+	vt823x_set_all_writes_to_lpc(dev);
+	w8326xx_memw_enable(0x2E);
 
-	/* Raise ROM MEMW# line on Winbond W83697 Super I/O. */
-	w836xx_ext_enter(0x2E);
-
-	if (!(wbsio_read(0x2E, 0x24) & 0x02))	/* Flash ROM enabled? */
-		wbsio_mask(0x2E, 0x24, 0x08, 0x08);	/* Enable MEMW#. */
-
-	w836xx_ext_leave(0x2E);
-
 	return 0;
 }
 
 /**
- * Suited for VIAs EPIA SP.
+ * Suited for VIAs EPIA SP and EPIA CN.
  */
 static int board_via_epia_sp(const char *name)
 {
 	struct pci_dev *dev;
-	uint8_t val;
 
 	dev = pci_dev_find(0x1106, 0x3227);	/* VT8237R ISA bridge */
 	if (!dev) {
@@ -232,15 +267,30 @@
 		return -1;
 	}
 
-	/* All memory cycles, not just ROM ones, go to LPC */
-	val = pci_read_byte(dev, 0x59);
-	val &= ~0x80;
-	pci_write_byte(dev, 0x59, val);
+	vt823x_set_all_writes_to_lpc(dev);
 
 	return 0;
 }
 
 /**
+ * Suited for Epox 8k5A2.
+ */
+static int board_epox_8k5a2(const char *name)
+{
+	struct pci_dev *dev;
+
+	dev = pci_dev_find(0x1106, 0x3177);	/* VT8235 ISA bridge */
+	if (!dev) {
+		fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
+		return -1;
+	}
+
+	w8326xx_memw_enable(0x2E);
+
+	return 0;
+}
+
+/**
  * Suited for ASUS P5A.
  *
  * This is rather nasty code, but there's no way to do this cleanly.
@@ -578,8 +628,6 @@
 {
 	struct pci_dev *dev;
 	uint8_t val;
-	uint32_t val2;
-	uint16_t port;
 
 	dev = pci_dev_find(0x1106, 0x3177);	/* VT8235 ISA bridge */
 	if (!dev) {
@@ -591,24 +639,9 @@
 	val &= 0x0c;
 	pci_write_byte(dev, 0x59, val);
 
-	/* We need the I/O Base Address for this board's flash enable. */
-	port = pci_read_word(dev, 0x88) & 0xff80;
+	vt823x_gpio_set(dev, 12, 1);
+	w8326xx_memw_enable(0x2E);
 
-	/* Starting at 'I/O Base + 0x4c' is the GPO Port Output Value.
-	 * We must assert GPO12 for our enable, which is in 0x4d.
-	 */
-	val2 = INB(port + 0x4d);
-	val2 |= 0x10;
-	OUTB(val2, port + 0x4d);
-
-	/* Raise ROM MEMW# line on Winbond W83697 Super I/O. */
-	w836xx_ext_enter(0x2e);
-	if (!(wbsio_read(0x2e, 0x24) & 0x02)) {	/* Flash ROM enabled? */
-		/* Enable MEMW# and set ROM size select to max. (4M). */
-		wbsio_mask(0x2e, 0x24, 0x28, 0x28);
-	}
-	w836xx_ext_leave(0x2e);
-
 	return 0;
 }
 
@@ -675,6 +708,7 @@
 	{0x10B9, 0x1541,      0,      0,  0x10B9, 0x1533,      0,      0, "asus",       "p5a",      "ASUS P5A",               board_asus_p5a},
 	{0x1166, 0x0205, 0x1014, 0x0347,       0,      0,      0,      0, "ibm",        "x3455",    "IBM x3455",              board_ibm_x3455},
 	{0x8086, 0x7110,      0,      0,  0x8086, 0x7190,      0,      0, "epox",       "ep-bx3",   "EPoX EP-BX3",            board_epox_ep_bx3},
+	{0x1106, 0x3177, 0x1106, 0x3177,  0x1106, 0x3059, 0x1695, 0x3005, NULL,         NULL,       "EPoX EP-8K5A2",          board_epox_8k5a2},
 	{0x8086, 0x1130,      0,      0,  0x105a, 0x0d30, 0x105a, 0x4d33, "acorp",      "6a815epd", "Acorp 6A815EPD",         board_acorp_6a815epd},
 	{0x1022, 0x2090,      0,      0,  0x1022, 0x2080,      0,      0, "artecgroup", "dbe61",    "Artec Group DBE61",      board_artecgroup_dbe6x},
 	{0x1022, 0x2090,      0,      0,  0x1022, 0x2080,      0,      0, "artecgroup", "dbe62",    "Artec Group DBE62",      board_artecgroup_dbe6x},
-------------- next part --------------
00:00.0 0600: 1106:3099
	Flags: bus master, 66MHz, medium devsel, latency 0
	Memory at d0000000 (32-bit, prefetchable) [size=128M]
	Capabilities: [a0] AGP version 2.0
	Capabilities: [c0] Power Management version 2
	Kernel driver in use: agpgart-via
	Kernel modules: via-agp

00:01.0 0604: 1106:b099 (prog-if 00 [Normal decode])
	Flags: bus master, 66MHz, medium devsel, latency 0
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
	I/O behind bridge: 0000c000-0000cfff
	Memory behind bridge: e8000000-e9ffffff
	Prefetchable memory behind bridge: d8000000-e7ffffff
	Capabilities: [80] Power Management version 2
	Kernel modules: shpchp

00:0a.0 0200: 10ec:8139 (rev 10)
	Subsystem: 10ec:8139
	Flags: bus master, medium devsel, latency 32, IRQ 10
	I/O ports at d000 [size=256]
	Memory at ea000000 (32-bit, non-prefetchable) [size=256]
	Capabilities: [50] Power Management version 2
	Kernel driver in use: 8139too
	Kernel modules: 8139too, 8139cp

00:10.0 0c03: 1106:3038 (rev 80) (prog-if 00 [UHCI])
	Subsystem: 1106:3038
	Flags: bus master, medium devsel, latency 32, IRQ 11
	I/O ports at d400 [size=32]
	Capabilities: [80] Power Management version 2
	Kernel driver in use: uhci_hcd
	Kernel modules: uhci-hcd

00:10.1 0c03: 1106:3038 (rev 80) (prog-if 00 [UHCI])
	Subsystem: 1106:3038
	Flags: bus master, medium devsel, latency 32, IRQ 5
	I/O ports at d800 [size=32]
	Capabilities: [80] Power Management version 2
	Kernel driver in use: uhci_hcd
	Kernel modules: uhci-hcd

00:10.2 0c03: 1106:3038 (rev 80) (prog-if 00 [UHCI])
	Subsystem: 1106:3038
	Flags: bus master, medium devsel, latency 32, IRQ 10
	I/O ports at dc00 [size=32]
	Capabilities: [80] Power Management version 2
	Kernel driver in use: uhci_hcd
	Kernel modules: uhci-hcd

00:10.3 0c03: 1106:3104 (rev 82) (prog-if 20 [EHCI])
	Subsystem: 1106:3104
	Flags: bus master, medium devsel, latency 32, IRQ 12
	Memory at ea001000 (32-bit, non-prefetchable) [size=256]
	Capabilities: [80] Power Management version 2
	Kernel driver in use: ehci_hcd
	Kernel modules: ehci-hcd

00:11.0 0601: 1106:3177
	Subsystem: 1106:3177
	Flags: bus master, stepping, medium devsel, latency 0
	Capabilities: [c0] Power Management version 2
	Kernel modules: i2c-viapro, via-ircc

00:11.1 0101: 1106:0571 (rev 06) (prog-if 8a [Master SecP PriP])
	Subsystem: 1106:0571
	Flags: bus master, medium devsel, latency 32, IRQ 11
	[virtual] Memory at 000001f0 (32-bit, non-prefetchable) [size=8]
	[virtual] Memory at 000003f0 (type 3, non-prefetchable) [size=1]
	[virtual] Memory at 00000170 (32-bit, non-prefetchable) [size=8]
	[virtual] Memory at 00000370 (type 3, non-prefetchable) [size=1]
	I/O ports at e000 [size=16]
	Capabilities: [c0] Power Management version 2
	Kernel driver in use: pata_via
	Kernel modules: pata_via, via82cxxx

00:11.5 0401: 1106:3059 (rev 50)
	Subsystem: 1695:3005
	Flags: medium devsel, IRQ 10
	I/O ports at e400 [size=256]
	Capabilities: [c0] Power Management version 2
	Kernel driver in use: VIA 82xx Audio
	Kernel modules: snd-via82xx

01:00.0 0300: 1002:4144 (prog-if 00 [VGA controller])
	Subsystem: 1002:0002
	Flags: bus master, stepping, 66MHz, medium devsel, latency 32, IRQ 11
	Memory at d8000000 (32-bit, prefetchable) [size=128M]
	I/O ports at c000 [size=256]
	Memory at e9000000 (32-bit, non-prefetchable) [size=64K]
	[virtual] Expansion ROM at e8000000 [disabled] [size=128K]
	Capabilities: [58] AGP version 2.0
	Capabilities: [50] Power Management version 2
	Kernel modules: radeonfb

01:00.1 0380: 1002:4164
	Subsystem: 1002:0003
	Flags: bus master, stepping, 66MHz, medium devsel, latency 32
	Memory at e0000000 (32-bit, prefetchable) [size=128M]
	Memory at e9010000 (32-bit, non-prefetchable) [size=64K]
	Capabilities: [50] Power Management version 2


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