[coreboot] [PATCH] Table code cleanup
Zheng.Bao at amd.com
Mon May 18 04:11:36 CEST 2009
1. We have disabled the display controller.
2. How is the region reserved? What can we do?
Sorry, I didn't trace the roadmap of HIGH_TABLE and have no idea about
what happened. I really need more help to solve this issue.
From: Myles Watson [mailto:mylesgw at gmail.com]
Sent: Friday, May 15, 2009 8:40 PM
To: Bao, Zheng; 'Patrick Georgi'
Subject: RE: [coreboot] [PATCH] Table code cleanup
> -----------output with HAVE_HIGH_TABLES ------------------
> High Tables Base is 7fff0000.
> Writing IRQ routing tables to 0x7fff0000...write_pirq_routing_table
> rom_table_end = 0x7fff38d0
> Adjust low_table_end from 0x00000818 to 0x00001000
> Adjust rom_table_end from 0x7fff38d0 to 0x80000000
> Adding high table area
> uma_memory_start=0x78000000, uma_memory_size=0x0
Maybe the problem is the UMA memory area? Is the size really zero? We
to fix this message and/or the UMA code. It looks like ACPI and UMA
> Wrote coreboot table at: 7fff38d0 - 7fff3ac8 checksum 4b5b
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