[coreboot] flashrom touches only 0x70000-0x80000 addresses of my bios flash
Luc Verhaegen
libv at skynet.be
Tue May 26 12:19:26 CEST 2009
On Tue, May 26, 2009 at 02:04:01PM +0400, Alexander Gordeev wrote:
> > > Could you please help me to solve this?
> >
> > We can try.
This is the board enable routine for this board (on top of the
standard chipset enable):
tmp = inb(0x14bf + 0x22);
outb(tmp, 0xEB); /* delay */
tmp &= ~0x0F;
tmp |= 0x05;
outb(tmp, 0x14bf + 0x22);
outb(tmp, 0xEB); /* delay */
This is the same as another report (another nvidia board), except for a
different IO offset (0x44C0 + 0x10):
http://tracker.coreboot.org/trac/coreboot/ticket/131
Can you provide the output of lspci -vvnxxx so that we:
* get device/subsystem id pairs for the board enable table.
* can spot the location of the pmio base address and make this function
useful for both cases.
Thanks,
Luc Verhaegen.
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