[coreboot] GeodeLX RAM initialisation issue
nathan at traverse.com.au
Thu Nov 5 13:42:40 CET 2009
Hi I am trying to sort out a RAM issue with coreboot on a motherboard we
have designed at my work.
The board uses the AMD LX800 and CS5536 companion chipset.
I have been using coreboot-v3 and based my board port on the Alix 1.C
code. We have a SODIMM socket, so I used the initram.c from the
amd/db800 code because it does SPD.
The symptoms are that sometimes a boot will die during disable_car() in
/* OK, here is the theory: we should be able to copy
* the data back over itself, and the wbinvd should then
* flush to memory. Let's see.
__asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE),
"S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory");
__asm__ __volatile__ ("wbinvd\n");
Sometimes it boots fine and appears to be quite stable. If I run
software like mprime95 to "Torture Test" the system, it doesn't fail.
However, there is one strange phenomenon that I've noticed. If I remove
the RTC battery backup and Linux forces a fsck because the last boot
time was in the future. If Linux fixes a couple of errors and reboots
automatically in 5 seconds, during the reboot it's almost guaranteed
that coreboot will get stuck in disable_car(). I don't know if this is
useful, or just a coincidence. In my build I have also disabled the
CMOS Option Table (CONFIG_OPTION_TABLE) in case something there might be
causing the problem.
Initially I thought it was a hardware problem with our PCBs, but have
tested with a bios chip from an AMD reference design board (EmbeddedBIOS
v5.3) which booted Linux fine without any problems, so I have concluded
that my problem must be something I'm doing (or not doing) in coreboot.
I have checked all the SPD values against the datasheet for the Hynix
RAM chips (256MiB 333MHz). I tried using the non-SPD method as in the
Alix 1.C code and specified all the RAM parameters. I have also tried
to follow sdram_enable() and other functions in
northbridge/amd/geodelx/raminit.c to check against the AMD LX databook's
section 6.1.3 BIOS Initialization Sequence, though I admit I could have
easily missed something here.
I would be most grateful of any suggestions for helping me work out
what's going wrong.
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