[PATCH 6/9] Properly mask value for MTRR mask.
Magnus Christensson
mch at virtutech.com
Thu Nov 5 10:23:26 CET 2009
---
src/mtrr.c | 14 ++++++++++++--
1 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/mtrr.c b/src/mtrr.c
index a9cd5f7..6bd0dba 100644
--- a/src/mtrr.c
+++ b/src/mtrr.c
@@ -29,7 +29,7 @@ void mtrr_setup(void)
if (CONFIG_COREBOOT)
return;
- u32 eax, ebx, ecx, cpuid_features;
+ u32 eax, ebx, ecx, edx, cpuid_features;
cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
if (!(cpuid_features & CPUID_MTRR))
return;
@@ -73,6 +73,16 @@ void mtrr_setup(void)
wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
/* Mark 3.5-4GB as UC, anything not specified defaults to WB */
wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0);
- wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800);
+
+ int phys_bits = 36;
+ cpuid(0x80000000u, &eax, &ebx, &ecx, &edx);
+ if (eax >= 0x80000008) {
+ /* Get physical bits from leaf 0x80000008 (if available) */
+ cpuid(0x80000008u, &eax, &ebx, &ecx, &edx);
+ phys_bits = eax & 0xff;
+ }
+ u64 phys_mask = ((1ull << phys_bits) - 1);
+ wrmsr_smp(MTRRphysMask_MSR(0), (~(0x20000000ull - 1) & phys_mask) | 0x800);
+
wrmsr_smp(MSR_MTRRdefType, 0xc06);
}
--
1.6.2.5
--------------020508030901070003090208
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