[coreboot] [v2] r4701 - trunk/coreboot-v2/src/mainboard/dell/s1850

svn at coreboot.org svn at coreboot.org
Thu Oct 1 17:59:50 CEST 2009


Author: rminnich
Date: 2009-10-01 17:59:49 +0200 (Thu, 01 Oct 2009)
New Revision: 4701

Modified:
   trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
   trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc
Log:
OK, this builds and even looks right. dell needs its own Makefile.inc because 
it is a P4 and it needs SSE for romcc not to go into infinite loop. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	2009-10-01 15:47:14 UTC (rev 4700)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	2009-10-01 15:59:49 UTC (rev 4701)
@@ -4,6 +4,7 @@
 	select CPU_INTEL_SOCKET_MPGA604
 	select NORTHBRIDGE_INTEL_E7520
 	select SOUTHBRIDGE_INTEL_I82801ER
+	select SOUTHBRIDGE_INTEL_PXHD
 	select SUPERIO_NSC_PC8374
 	select PIRQ_TABLE
 	help

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc	2009-10-01 15:47:14 UTC (rev 4700)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc	2009-10-01 15:59:49 UTC (rev 4701)
@@ -18,5 +18,46 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-include $(src)/mainboard/Makefile.romccboard.inc
+initobj-y += crt0.o
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/cpu_reset.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += failover.inc
+crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
+crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
+crt0-y += ../../../../src/cpu/x86/sse/enable_sse.inc
+crt0-y += auto.inc
+crt0-y += ../../../../src/cpu/x86/sse/disable_sse.inc
+crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
 
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+driver-y += mainboard.o
+
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+
+ifdef POST_EVALUATION
+
+ROMCCFLAGS ?= -mcpu=p4
+
+$(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c
+	$(obj)/romcc $(ROMCCFLAGS) -O2 --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@
+
+ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+	$(obj)/romcc $(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+else
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c
+	$(obj)/romcc $(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+endif
+
+endif
+





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