[coreboot] [v2] r4745 - in trunk/coreboot-v2/src/cpu/intel: socket_PGA370 socket_mPGA479M socket_mPGA604
rminnich at gmail.com
Fri Oct 9 05:44:18 CEST 2009
On Thu, Oct 8, 2009 at 5:26 PM, Stefan Reinauer <stepan at coresystems.de> wrote:
> Isn't MMX or SSE something attached to a given CPU rather than a socket?
The current design sets the choice of mmx/sse in the *mainboard* by
the inclusion of .inc files.
Moving it to the socket is a bit better than that.
If a socket includes multiple CPU types, is there ever a case where
different CPUs for that socket have different
settings for MMX and SSE? If so, then every mainboard in v2 has been
wrong until now. If not, then it is ok to set MMX/SSE in the socket.
It gets worse! For a given socket, you have to use the *least* set of
capabilities. CPUs with less capabilities have "veto power" over CPUs
with more capabilities, because you have to generate romcc code that
will work on the least-capable CPU for that socket. So, if ANY cpu in
a given socket doesn't have SSE, you're going to have to disable ALL
SSE code in ROMCC for that socket, because you are allowing people to
plug in CPUs with or without SSE, and you can't "un-use" the SSE usage
in the ROMCC code. Which means that the socket has to determine
whether MMX and SSE are set.
I hope this makes sense, I'm tired.
Bottom line, however: the socket determines usage of SSE and MMX, not
the CPU, because at the socket level you know which CPU types to
support, but at the CPU level you don't.
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