[coreboot] [v2] r4745 - in trunk/coreboot-v2/src/cpu/intel: socket_PGA370 socket_mPGA479M socket_mPGA604
c-d.hailfinger.devel.2006 at gmx.net
Sat Oct 10 17:53:00 CEST 2009
On 10.10.2009 17:31, Peter Stuge wrote:
> Stefan Reinauer wrote:
>>>> Enabling MMX and SSE per socket is only needed because romcc ne
>>>> to work without cache or memory.
>>> So far that's the only use, but that can change of course.
>> I don't think it can. Nor should it. Any other use of SSE or MMX in
>> the firmware would be a very bad move.
> Hm, why is that? If some code for a component which is known to have
> SSE - why not? It would basically mean -msse for gcc.
MOVNTQ and family, MMX memory ops and SSE memory ops are not allowed in
CAR unless you deliberately want to access RAM instead of CAR. The AMD
BKDG has the details.
> Oh, just saw something at Apple.
> in the SSE section:
> "SSE is enabled by default on gcc-4.0."
> Don't know if that applies also to upstream gcc. Probably not.
Does that mean we have to disable SSE explicitly if we compile the CAR
stage of coreboot on such GCC versions?
Developer quote of the week:
"We are juggling too many chainsaws and flaming arrows and tigers."
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