[coreboot] [v2] r4787 - in trunk/coreboot-v2/src/mainboard/tyan: s2891 s2892 s2895

svn at coreboot.org svn at coreboot.org
Fri Oct 16 16:34:50 CEST 2009


Author: myles
Date: 2009-10-16 16:34:50 +0200 (Fri, 16 Oct 2009)
New Revision: 4787

Modified:
   trunk/coreboot-v2/src/mainboard/tyan/s2891/acpi_tables.c
   trunk/coreboot-v2/src/mainboard/tyan/s2892/acpi_tables.c
   trunk/coreboot-v2/src/mainboard/tyan/s2895/acpi_tables.c
Log:
Fix IRQ9 and allow ACPI without an MP table for Tyan s289x.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/acpi_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/acpi_tables.c	2009-10-16 13:34:32 UTC (rev 4786)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/acpi_tables.c	2009-10-16 14:34:50 UTC (rev 4787)
@@ -42,6 +42,20 @@
 		apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf;
 		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4,
 						   apic_addr, 0);
+		/* Initialize interrupt mapping if mptable.c didn't. */
+		#if (!CONFIG_GENERATE_MP_TABLE)
+		{
+			u32 dword;
+			dword = 0x0120d218;
+			pci_write_config32(dev, 0x7c, dword);
+
+			dword = 0x12008a00;
+			pci_write_config32(dev, 0x80, dword);
+
+			dword = 0x0000007d;
+			pci_write_config32(dev, 0x84, dword);
+		}
+		#endif
 	}
 
 	/* Write AMD 8131 two IOAPICs. */
@@ -59,9 +73,9 @@
 						   apic_addr, 0x1C);
 	}
 
-	/* IRQ9 ACPI active low. */
+	/* IRQ9 */
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
+		current, 0, 9, 9, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW);
 
 	/* 0: mean bus 0--->ISA */
 	/* 0: PIC 0 */

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/acpi_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/acpi_tables.c	2009-10-16 13:34:32 UTC (rev 4786)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/acpi_tables.c	2009-10-16 14:34:50 UTC (rev 4787)
@@ -42,6 +42,20 @@
 		apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf;
 		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4,
 						   apic_addr, 0);
+		/* Initialize interrupt mapping if mptable.c didn't. */
+		#if (!CONFIG_GENERATE_MP_TABLE)
+		{
+			u32 dword;
+			dword = 0x0120d218;
+			pci_write_config32(dev, 0x7c, dword);
+
+			dword = 0x12008a00;
+			pci_write_config32(dev, 0x80, dword);
+
+			dword = 0x0000007d;
+			pci_write_config32(dev, 0x84, dword);
+		}
+		#endif
 	}
 
 	/* Write AMD 8131 two IOAPICs. */
@@ -59,9 +73,9 @@
 						   apic_addr, 0x1C);
 	}
 
-	/* IRQ9 ACPI active low. */
+	/* IRQ9 */
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
+		current, 0, 9, 9, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW);
 
 	/* 0: mean bus 0--->ISA */
 	/* 0: PIC 0 */

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/acpi_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/acpi_tables.c	2009-10-16 13:34:32 UTC (rev 4786)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/acpi_tables.c	2009-10-16 14:34:50 UTC (rev 4787)
@@ -42,6 +42,20 @@
 		apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf;
 		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4,
 						   apic_addr, 0);
+		/* Initialize interrupt mapping if mptable.c didn't. */
+		#if (!CONFIG_GENERATE_MP_TABLE)
+		{
+			u32 dword;
+			dword = 0x0120d218;
+			pci_write_config32(dev, 0x7c, dword);
+
+			dword = 0x12008a00;
+			pci_write_config32(dev, 0x80, dword);
+
+			dword = 0x00080d7d;
+			pci_write_config32(dev, 0x84, dword);
+		}
+		#endif
 	}
 
 	/* Write AMD 8131 two IOAPICs. */
@@ -65,11 +79,25 @@
 		apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf;
 		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 7,
 						   apic_addr, 0x20);
+		/* Initialize interrupt mapping if mptable.c didn't. */
+		#if (!CONFIG_GENERATE_MP_TABLE)
+		{
+			u32 dword;
+			dword = 0x0000d218; // Why does the factory BIOS have 0?
+			pci_write_config32(dev, 0x7c, dword);
+
+			dword = 0x00000000;
+			pci_write_config32(dev, 0x80, dword);
+
+			dword = 0x00000d00; // Same here.
+			pci_write_config32(dev, 0x84, dword);
+		}
+		#endif
 	}
 
-	/* IRQ9 ACPI active low. */
+	/* IRQ9 */
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
+		current, 0, 9, 9, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW);
 
 	/* IRQ0 -> APIC IRQ2. */
 	/* Doesn't work on this board. */





More information about the coreboot mailing list