[coreboot] [Fwd: Re: [Fwd: Re: arima hdama problem]]

[Hugh Greenberg]

Below is the output with the no_smp patch and the previous patch.  Is 
there another problem since the payload is not being loaded?

coreboot-2.3 Tue Oct 20 16:46:25 MDT 2009 starting...
Enabling routing table for node 00 done.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done
started ap apicid:
SBLink=00
NC node|link=00
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x35
freq_cap1=0x35, freq_cap2=0x15
dev1 old_freq=0x0, freq=0x4, needs_reset=0x1
dev2 old_freq=0x0, freq=0x4, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
entering ht_optimize_link
pos=0xd2, unfiltered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x1
pos=0xce, filtered freq_cap=0x1
freq_cap1=0x15, freq_cap2=0x1
dev1 old_freq=0x0, freq=0x0, needs_reset=0x0
dev2 old_freq=0x0, freq=0x0, needs_reset=0x0
width_cap1=0x0, width_cap2=0x0
dev1 input ln_width1=0x3, ln_width2=0x3
dev1 input width=0x0
dev1 output ln_width1=0x3, ln_width2=0x3
dev1 input|output width=0x0
old dev1 input|output width=0x0
dev2 input|output width=0x0
old dev2 input|output width=0x0
ht reset -


coreboot-2.3 Tue Oct 20 16:46:25 MDT 2009 starting...
Enabling routing table for node 00 done.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done
started ap apicid:
SBLink=00
NC node|link=00
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x35
freq_cap1=0x35, freq_cap2=0x15
dev1 old_freq=0x4, freq=0x4, needs_reset=0x0
dev2 old_freq=0x4, freq=0x4, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
entering ht_optimize_link
pos=0xd2, unfiltered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x1
pos=0xce, filtered freq_cap=0x1
freq_cap1=0x15, freq_cap2=0x1
dev1 old_freq=0x0, freq=0x0, needs_reset=0x0
dev2 old_freq=0x0, freq=0x0, needs_reset=0x0
width_cap1=0x0, width_cap2=0x0
dev1 input ln_width1=0x3, ln_width2=0x3
dev1 input width=0x0
dev1 output ln_width1=0x3, ln_width2=0x3
dev1 input|output width=0x0
old dev1 input|output width=0x0
dev2 input|output width=0x0
old dev2 input|output width=0x0
SMBus controller enabled
Ram1.00
setting up CPU00 northbridge registers
done.
Ram2.00
Enabling dual channel memory
Registered
166Mhz
RAM end at 0x00100000 kB
Lower RAM end at 0x00100000 kB
Ram3
Before starting clocks: Before memreset: cpu is pre_c0
after first udelay
after second udelay
Before controllers loop: ECC enabled
Before 2nd controllers loop: Initializing memory:  done
Before hole: Ram4
v_esp=000cedb8
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Jumping to image.
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
Stage: load fallback/coreboot_ram @ 1048576/245760 bytes, enter @ 100000
Stage: done loading.
Jumping to image.
POST: 0x80
POST: 0x39
coreboot-2.3 Tue Oct 20 16:46:25 MDT 2009 booting...
POST: 0x40
Enumerating buses...
Show all devs...Before Device Enumeration.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:18.0: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:00.1: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:01.1: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:00.1: enabled 1, 0 resources
PCI: 00:00.2: enabled 0, 0 resources
PCI: 00:01.0: enabled 0, 0 resources
PCI: 00:06.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.1: enabled 0, 2 resources
PNP: 002e.2: enabled 0, 2 resources
PNP: 002e.3: enabled 1, 2 resources
PNP: 002e.4: enabled 0, 0 resources
PNP: 002e.5: enabled 0, 0 resources
PNP: 002e.6: enabled 1, 3 resources
PNP: 002e.7: enabled 0, 0 resources
PNP: 002e.8: enabled 0, 0 resources
PNP: 002e.9: enabled 0, 0 resources
PNP: 002e.a: enabled 0, 0 resources
PCI: 00:01.1: enabled 1, 0 resources
PCI: 00:01.2: enabled 1, 0 resources
PCI: 00:01.3: enabled 1, 0 resources
I2C: 00:70: enabled 1, 0 resources
I2C: 00:2c: enabled 1, 0 resources
I2C: 00:50: enabled 1, 0 resources
I2C: 00:51: enabled 1, 0 resources
I2C: 00:52: enabled 1, 0 resources
I2C: 00:53: enabled 1, 0 resources
I2C: 00:54: enabled 1, 0 resources
I2C: 00:55: enabled 1, 0 resources
I2C: 00:56: enabled 1, 0 resources
I2C: 00:57: enabled 1, 0 resources
PCI: 00:01.5: enabled 0, 0 resources
PCI: 00:01.6: enabled 1, 0 resources
PCI: 00:18.1: enabled 1, 0 resources
PCI: 00:18.2: enabled 1, 0 resources
PCI: 00:18.3: enabled 1, 0 resources
PCI: 00:19.0: enabled 1, 0 resources
PCI: 00:19.1: enabled 1, 0 resources
PCI: 00:19.2: enabled 1, 0 resources
PCI: 00:19.3: enabled 1, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
 APIC_CLUSTER: 0: enabled 1, 0 resources
  APIC: 00: enabled 1, 0 resources
 PCI_DOMAIN: 0000: enabled 1, 0 resources
  PCI: 00:18.0: enabled 1, 0 resources
   PCI: 00:00.0: enabled 1, 0 resources
   PCI: 00:00.1: enabled 1, 0 resources
   PCI: 00:01.0: enabled 1, 0 resources
   PCI: 00:01.1: enabled 1, 0 resources
   PCI: 00:00.0: enabled 1, 0 resources
    PCI: 00:00.0: enabled 1, 0 resources
    PCI: 00:00.1: enabled 1, 0 resources
    PCI: 00:00.2: enabled 0, 0 resources
    PCI: 00:01.0: enabled 0, 0 resources
    PCI: 00:06.0: enabled 1, 0 resources
   PCI: 00:01.0: enabled 1, 0 resources
    PNP: 002e.0: enabled 0, 3 resources
    PNP: 002e.1: enabled 0, 2 resources
    PNP: 002e.2: enabled 0, 2 resources
    PNP: 002e.3: enabled 1, 2 resources
    PNP: 002e.4: enabled 0, 0 resources
    PNP: 002e.5: enabled 0, 0 resources
    PNP: 002e.6: enabled 1, 3 resources
    PNP: 002e.7: enabled 0, 0 resources
    PNP: 002e.8: enabled 0, 0 resources
    PNP: 002e.9: enabled 0, 0 resources
    PNP: 002e.a: enabled 0, 0 resources
   PCI: 00:01.1: enabled 1, 0 resources
   PCI: 00:01.2: enabled 1, 0 resources
   PCI: 00:01.3: enabled 1, 0 resources
    I2C: 00:70: enabled 1, 0 resources
     I2C: 00:2c: enabled 1, 0 resources
    I2C: 00:50: enabled 1, 0 resources
    I2C: 00:51: enabled 1, 0 resources
    I2C: 00:52: enabled 1, 0 resources
    I2C: 00:53: enabled 1, 0 resources
    I2C: 00:54: enabled 1, 0 resources
    I2C: 00:55: enabled 1, 0 resources
    I2C: 00:56: enabled 1, 0 resources
    I2C: 00:57: enabled 1, 0 resources
   PCI: 00:01.5: enabled 0, 0 resources
   PCI: 00:01.6: enabled 1, 0 resources
  PCI: 00:18.1: enabled 1, 0 resources
  PCI: 00:18.2: enabled 1, 0 resources
  PCI: 00:18.3: enabled 1, 0 resources
  PCI: 00:19.0: enabled 1, 0 resources
  PCI: 00:19.1: enabled 1, 0 resources
  PCI: 00:19.2: enabled 1, 0 resources
  PCI: 00:19.3: enabled 1, 0 resources
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
  PCI: 00:18.3 siblings=0
CPU: APIC: 00 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
PCI: 00:18.0 [1022/1100] bus ops
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] ops
PCI: 00:18.3 [1022/1103] enabled
PCI: 00:18.4, bad id 0xffffffff
PCI: 00:18.5, bad id 0xffffffff
PCI: 00:18.6, bad id 0xffffffff
PCI: 00:18.7, bad id 0xffffffff
Disabling static device: PCI: 00:19.0
Disabling static device: PCI: 00:19.1
Disabling static device: PCI: 00:19.2
Disabling static device: PCI: 00:19.3
PCI: 00:19.4, bad id 0xffffffff
PCI: 00:19.5, bad id 0xffffffff
PCI: 00:19.6, bad id 0xffffffff
PCI: 00:19.7, bad id 0xffffffff
PCI: 00:1a.0, bad id 0xffffffff
PCI: 00:1b.0, bad id 0xffffffff
PCI: 00:1c.0, bad id 0xffffffff
PCI: 00:1d.0, bad id 0xffffffff
PCI: 00:1e.0, bad id 0xffffffff
PCI: 00:1f.0, bad id 0xffffffff
POST: 0x25

-- 
Hugh Greenberg


>
>
> On Tue, Oct 20, 2009 at 3:58 PM, Hugh Greenberg <hng at lanl.gov 
> <mailto:hng at lanl.gov>> wrote:
>
>     Seems to have gotten farther:
>
>
> OK.  So for some reason you can't read the LAPIC.  I have no idea why 
> that could be.
>
> Anyone else wnat to chime in?  His board hangs in udelay(), which just 
> does lapi_read in a loop.
>
>  start = lapic_read(LAPIC_TMCCT);
>     do {
>         value = lapic_read(LAPIC_TMCCT);
>     } while((start - value) < ticks);
>
> If I make it time out after 1000000 reads, it continues, otherwise it 
> hangs.
>
> The only thing I can think is that the timer didn't get initialized.  
> But I don't know why it would hang later.  Maybe we should try no_smp 
> with the workaround.
>
> Patch attached to initialize the timer.
>
> Thanks,
> Myles
>