[coreboot] BIOS RAM in AMD SB7XX southbridges ?

[Gregg Levine]

On Tue, Oct 27, 2009 at 4:51 PM, David Hendricks <dhendrix at google.com> wrote:
> On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun
> <darmawan.salihun at gmail.com> wrote:
>>
>> What is the BIOS RAM in AMD SB7XX used for?
>
> Looks like scratchpad memory to me. From the public doc:
>
> 3.3 BIOS RAM
> The SB700 has 256 bytes of BIOS RAM. Data in this RAM is preserved until
> RSMRST# or S5 is
> asserted, or until power is lost.
> This RAM is accessed using index and data registers at CD4h/CD5h.
>
> Might it be enough to act as a very, very small cache-as-RAM substitute
> until CAR can be set up?
>
> On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun
> <darmawan.salihun at gmail.com> wrote:
>>
>> Is it to buffer the BIOS contents from SPI flash chip prior to
>> execution of the very first instruction?
>> I recall that it's impossible to execute code directly in an SPI chip.
>
> That's correct, afaik.
> --
> David Hendricks (dhendrix)
> Systems Software Engineer, Google Inc.
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

Hello!
This is well and good David. Thank you!
And as it happens Google Mail goofed on its spam scanning, and even
mistook this one for a phishing scheme. According to other folk at
Google they themselves obviously use the Google Mail service
internally, so I do not see why this would have happened.

-----
Gregg C Levine gregg.drwho8 at gmail.com
"This signature was once found posting rude
 messages in English in the Moscow subway."