[coreboot] unstable AMD Fam10h boot

[Marc Jones]

On Sun, Sep 6, 2009 at 4:32 PM, ron minnich<rminnich at gmail.com> wrote:
> The way I see it the memory setup and SMP support in CAR are two very
> different issues.

This bug is totally my fault...

Yes,  Memory setup and SMP CAR are two different issues. The SMP setup
happens during CAR is to setup microcode, HT and FIDVID prior to the
PLL reset and memory setup.

All the SMP PCI config space access should be MMIO. It is the first
thing that is enabled in CPU init in set_pci_mmio_conf_reg().

The bug is that I mixed a mem setup function in with SMP setup by
using mctGetLogicalCPUID() which uses Get_NB32. As pointed out, the
GET_NB32 is a cf8/cfc function. The mct code ported from AGESA assumes
that it is running on the BSP only and uses cf8/cfc..... (historical
k8 bug I think)

I think that I should change the mct PCI config functions to call the
coreboot pci_read_config32 functions that handle MMIO vs cfc/cf8
nicely. This should future proof  mct functions in CAR and a step
toward SMP memory setup.

Some of that mct code PCI config space code is a little funny (ok, a
lot funny), so it will take a little care. I should be able work patch
in a couple of days.

Marc

-- 
http://marcjonesconsulting.com