[coreboot] unstable AMD Fam10h boot

[Stefan Reinauer]

Peter Stuge wrote:
> Stefan Reinauer wrote:
>   
>>> RAM init working concurrently with multiple memory controllers -
>>> they're on PCI, right?
>>>       
>> Yes.
>>
>> But why would it not be completely sufficient to set up all ram
>> controllers in the system from the BSP?
>>     
>
> The big coreboot SMP win is with ECC scrubbing, right? 
Yes, but that does not happen until we're in stage2. It's not really
part of memory init.

> Does that
> involve some PCI config space accesses to the memory controllers?
>   
I don't think so.