[coreboot] unstable AMD Fam10h boot

[Eric W. Biederman]

ron minnich <rminnich at gmail.com> writes:

> The way I see it the memory setup and SMP support in CAR are two very
> different issues.
>
> BSP can do its own memory. Once that memory is set up the APs can use
> it. Thus, the APs can have working memory when they do their RAM
> setup. In other words,
> BSP does RAM setup in CAR
> APs can do RAM setup with working RAM -- they just use the BSP RAM,
> which is working.
>
> The K8 code hints of this model, and, when I did my trial code for V3,
> this is how I set it up to work.
>
> Hence, we can do SMP memory setup  as long as the BSP sets up its own
> memory before it starts up the APs. We are really talking about SMP in
> CAR, which seems like a much harder issue.
>
> Make sense? Something I'm missing?

Long ago and far away.  When I did the K8 code here is what I recall
of my reasoning.

The only operation that benefited from being parallel was the clearing
ECC memory so it had consistent ECC bits.  Everything else works just
dandy from the BSP, and in fact because of the way the K8 memory
layout works you have to do all of the heavy lifting on a single cpu
so that you can place all of memory into one nice area for the mtrrs
and the like.

If the K10 has gotten as far as true cpu hotoplug support things may
be more decoupled now but I would be surprised if that mattered in
any real configuration.

The only thing that I ever had the other cpus starting earlier for
and this was pretty fundamental was to assign them their local apic
id's and put them to sleep.  After making that code work I never
put a print statement in there or did anything fancy.  There is just
nothing in there to make parallelism any more than an nuisance.

A big chunk of what has to happen very early is setting up hypertransport
and enabling routing between the cpus.  As I recall some point at the
end of setting up hypertransport routing the secondary cpus all come
online.  

With the K7 AMD actually had a model where both of the cpus started
booting at once and you read a northbridge register to see which one
should be primary the first read of that register returned 0 all
subsequent reads return 1 (or visa versa).  If you didn't read that
register first you got to sleep.  The K8 had a very similar model
except only one processor was every connected up as a bootstrap
processor in practice, and if you aren't connected up as a bootstrap
processor you sleep until the bootsrap processor setups up your
hypertransport.

SMP in coreboot (except where required) is a bad idea.  There are no
performance wins (unless you need to initialize memory with writes)
and it is an unnecessary complication.  So konk the other cpus on
the head as quickly as you can and go single processor.

Eric