[coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx

[Paul Menzel]

Dear Joseph,


Am Donnerstag, den 08.04.2010, 02:09 -0400 schrieb Joseph Smith:
> 1. This patch adds CAR for Intel P6 series processors.
> 2. Add support for Micro-FCBGA 479 Celeron and PIII's
> 3. Add support for model_6bx and microcode updates
> 4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson IP1000

sorry for my dump question. Does supporting CAR have any practical
improvements besides going with coreboot features(?). For example did
boot time improve?

> Build and boot tested (bootlog attached).

It says »Boot failed.« at the end. But that is due to the payload, is
not it?

Anyway, I just spotted one indentation error. Someone knowledgeable has
to do the review. Sorry!

[…]

> Index: src/cpu/intel/model_6bx/cache_as_ram_disable.c
> ===================================================================
> --- src/cpu/intel/model_6bx/cache_as_ram_disable.c      (revision 0)
> +++ src/cpu/intel/model_6bx/cache_as_ram_disable.c      (revision 0)
> @@ -0,0 +1,89 @@
> +/*
> + * This file is part of the coreboot project.
> + * 
> + * Copyright (C) 2007-2009 coresystems GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; version 2 of
> + * the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include "cpu/x86/car/copy_and_run.c"
> +
> +/* called from assembler code */
> +void stage1_main(unsigned long bist);
> +
> +/* from romstage.c */
> +void real_main(unsigned long bist);
> +
> +void stage1_main(unsigned long bist)
> +{
> +       unsigned int cpu_reset = 0;
> +
> +       real_main(bist);
> +
> +       /* No servicable parts below this line .. */
> +#ifdef CAR_DEBUG
> +        /* Check value of esp to verify if we have enough rom for
> stack in Cache as RAM */
> +       unsigned v_esp;
> +       __asm__ volatile (
> +               "movl   %%esp, %0\n"
> +               : "=a" (v_esp)
> +       );
> +       printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
> +#endif
> +
> +        printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset);
> +       printk(BIOS_SPEW, "No cache as ram now - ");

This indentation looks different. I do not know if it is just my MUA.

[…]


Thanks for your work,

Paul


[1] http://www.coreboot.org/images/6/6c/LBCar.pdf
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