[coreboot] [PATCH] 440BX raminit cleanup

[Keith Hui]

Attached patch does the following on 440BX RAM init code:
1. Restore DUMPNORTH() macro. dump_pci_device() never really went
away, as romstages for all 440BX boards included lib/debug.c required
for it.
2. Move the NB macro up and changed DUMPNORTH() to use it as well.
3. Resolves a number of TODO items. That also means filling in some
additional register descriptions marked as such.
4. Change register_values[] static array from array of long to array
of u8. Takes up only 1/4 of previous size and still do the same thing.
5. Remove the extra line that unconditionally sets SDRAMPWR, which is
just wrong now that it is contained in register_values[] array and
properly conditioned by a config option.
6. Small cosmetic tidy-ups.

If I have submitted a previous patch for the same (I don't even
remember now :-O), this patch supersedes it.

abuild-tested on all 440BX targets. Boot tested on P2B-LS.

Signed-off-by: Keith Hui <buurin at gmail.com>

romstage boot log with detailed RAM init debug enabled:

coreboot-4.0-r5383M Thu Apr  8 23:21:32 EDT 2010 starting...
SMBus controller enabled
Northbridge prior to SDRAM init:
PCI: 00:00.00
00: 86 80 90 71 06 00 10 22 03 00 00 06 00 00 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 04 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00
60: 01 01 01 01 01 01 01 01 00 00 00 00 00 00 00 00
70: 00 1f 02 38 00 00 00 00 00 00 00 38 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 80 00 00 00 04 61 00 00 00 05 00 00 00 00 00 00
a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 18 0c 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 f8 00 00 20 0f 00 00 00 00 00 00
Found DIMM in slot 00
Found DIMM in slot 01
PGPOL[BPR] has been set to 0x0f
RPS has been set to 0x00a5
NBXECC[31:24] has been set to 0xff
DRAMC has been set to 0x08
RAM Enable 1: Apply NOP
RAM Enable 2: Precharge all
RAM Enable 3: CBR
RAM Enable 4: Mode register set
RAM Enable 5: Normal operation
RAM Enable 6: Enable refresh
    Enabling refresh (DRAMC = 0x09) for DIMM 00
    Enabling refresh (DRAMC = 0x09) for DIMM 01
Northbridge following SDRAM init:
PCI: 00:00.00
00: 86 80 90 71 06 00 10 22 03 00 00 06 00 00 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 0c 80 00 ff 00 00 00 09 03 30 33 33 33 33 33 33
60: 08 10 20 30 30 30 30 30 00 ec 2b 00 a0 ba 00 00
70: 00 1f 02 38 a5 00 10 00 00 0f 10 38 10 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 80 00 00 00 04 61 00 00 00 05 00 00 00 00 00 00
a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 18 0c e4 ff 5f 00 00 00
d0: 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 f8 00 00 20 0f 00 00 00 00 00 00
Testing DRAM : 00000000-000a0000
DRAM fill: 00000000-000a0000
000a0000
DRAM filled
DRAM verify: 00000000-000a0000
000a0000
DRAM range verified.
Done.
Copying coreboot to RAM.
Loading stage image.
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.
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