[coreboot] [commit] r5412 - in trunk/src: cpu/intel/model_6ex mainboard/kontron/986lcd-m mainboard/roda/rk886ex
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svn at coreboot.org
Tue Apr 13 01:04:29 CEST 2010
Author: stepan
Date: Tue Apr 13 01:04:29 2010
New Revision: 5412
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5412
Log:
move model_6ex car to a single file. No more .c files that only consist of a
single several pages long asm statement
Could use some renumbering of post codes, but that's good for another time.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>
Deleted:
trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c
trunk/src/cpu/intel/model_6ex/cache_as_ram_post.c
Modified:
trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
trunk/src/mainboard/kontron/986lcd-m/romstage.c
trunk/src/mainboard/roda/rk886ex/romstage.c
Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Mon Apr 12 17:28:34 2010 (r5411)
+++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Tue Apr 13 01:04:29 2010 (r5412)
@@ -137,12 +137,142 @@
post_code(0x23)
- call stage1_main
+ /* Call romstage.c main function */
+ call main
post_code(0x2f)
-error:
+
+ post_code(0x30)
+
+ /* Disable Cache */
+ movl %cr0, %eax
+ orl $(1 << 30), %eax
+ movl %eax, %cr0
+
+ post_code(0x31)
+
+ /* Disable MTRR */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ andl $(~(1 << 11)), %eax
+ wrmsr
+
+ post_code(0x31)
+
+ invd
+#if 0
+ xorl %eax, %eax
+ xorl %edx, %edx
+ movl $MTRRphysBase_MSR(0), %ecx
+ wrmsr
+ movl $MTRRphysMask_MSR(0), %ecx
+ wrmsr
+ movl $MTRRphysBase_MSR(1), %ecx
+ wrmsr
+ movl $MTRRphysMask_MSR(1), %ecx
+ wrmsr
+#endif
+
+ post_code(0x33)
+
+#undef CLEAR_FIRST_1M_RAM
+#ifdef CLEAR_FIRST_1M_RAM
+ post_code(0x34)
+ /* Enable Write Combining and Speculative Reads for the first 1MB */
+ movl $MTRRphysBase_MSR(0), %ecx
+ movl $(0x00000000 | MTRR_TYPE_WRCOMB), %eax
+ xorl %edx, %edx
+ wrmsr
+ movl $MTRRphysMask_MSR(0), %ecx
+ movl $(~(1024*1024 -1) | (1 << 11)), %eax
+ movl $0x0000000f, %edx // 36bit address space
+ wrmsr
+ post_code(0x35)
+#endif
+
+ /* Enable Cache */
+ movl %cr0, %eax
+ andl $~( (1 << 30) | (1 << 29) ), %eax
+ movl %eax, %cr0
+
+
+ post_code(0x36)
+#ifdef CLEAR_FIRST_1M_RAM
+
+ /* Clear first 1MB of RAM */
+ movl $0x00000000, %edi
+ cld
+ xorl %eax, %eax
+ movl $((1024*1024) / 4), %ecx
+ rep stosl
+
+ post_code(0x37)
+#endif
+
+ /* Disable Cache */
+ movl %cr0, %eax
+ orl $(1 << 30), %eax
+ movl %eax, %cr0
+
+ post_code(0x38)
+
+ /* Enable Write Back and Speculative Reads for the first 1MB */
+ movl $MTRRphysBase_MSR(0), %ecx
+ movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
+ xorl %edx, %edx
+ wrmsr
+ movl $MTRRphysMask_MSR(0), %ecx
+ movl $(~(1024*1024 -1) | (1 << 11)), %eax
+ movl $0x0000000f, %edx // 36bit address space
+ wrmsr
+
+ post_code(0x39)
+
+ /* And Enable Cache again after setting MTRRs */
+ movl %cr0, %eax
+ andl $~( (1 << 30) | (1 << 29) ), %eax
+ movl %eax, %cr0
+
+ post_code(0x3a)
+
+ /* Enable MTRR */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ orl $(1 << 11), %eax
+ wrmsr
+
+ post_code(0x3b)
+
+ /* Invalidate the cache again */
+ invd
+
+
+ /* clear boot_complete flag */
+ xorl %ebp, %ebp
+__main:
+ post_code(0x11)
+ cld /* clear direction flag */
+
+ movl %ebp, %esi
+
+ /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This
+ * makes sure that we stay completely within the 1M-64K of memory that we
+ * preserve for suspend/resume.
+ */
+
+#ifndef HIGH_MEMORY_SAVE
+#warning Need a central place for HIGH_MEMORY_SAVE
+#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 )
+#endif
+ movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp
+ movl %esp, %ebp
+ pushl %esi
+ call copy_and_run
+
+.Lhlt:
+ post_code(0xee)
hlt
- jmp error
+ jmp .Lhlt
mtrr_table:
/* Fixed MTRRs */
Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/romstage.c Mon Apr 12 17:28:34 2010 (r5411)
+++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Tue Apr 13 01:04:29 2010 (r5412)
@@ -359,9 +359,7 @@
//
#include "lib/cbmem.c"
-#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
-
-void real_main(unsigned long bist)
+void main(unsigned long bist)
{
u32 reg32;
int boot_mode = 0;
Modified: trunk/src/mainboard/roda/rk886ex/romstage.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/romstage.c Mon Apr 12 17:28:34 2010 (r5411)
+++ trunk/src/mainboard/roda/rk886ex/romstage.c Tue Apr 13 01:04:29 2010 (r5412)
@@ -272,9 +272,8 @@
// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
//
#include "lib/cbmem.c"
-#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
-void real_main(unsigned long bist)
+void main(unsigned long bist)
{
u32 reg32;
int boot_mode = 0;
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