[coreboot] DL145 G1 with dual dualcore CPU using coreboot ?
enok at lysator.liu.se
Tue Aug 17 14:52:15 CEST 2010
Carl-Daniel Hailfinger wrote:
> On 16.08.2010 21:15, Myles Watson wrote:
>>> The memory problem remains though. If only that can be solved, then I'm
>>> basically satisfied. Any hints?
>>>> Have you tried different configurations? Coreboot is only seeing the
>>>> RAM on node 0. Where is the RAM on your board?
>>> I use four 512MB DIMM's, two on each CPU, so there is one DIMM per
>>> channel. The DIMM's on CPU 0 are detected but the DIMM's on CPU 1 are
>> It's possible that there is a mux in the way that needs to be set up
>> correctly to allow you to read the DIMMs on the other CPU.
>>> If I move all four DIMM's to CPU0 then coreboot detects 2GB but
>>> hangs when initializing the memory.
>> That sounds like a different problem. Maybe the mux idea isn't right.
> Very odd. Enabling DRAM debugging is a good idea.
> By the way, please check if the SPDs for all DIMMs match. If the DIMMs
> are just compatible and not identical, coreboot may have problems
> detecting all RAM. OTOH, if all visible (from a SPD perspective) DIMMs
> are also present in the computed memory count, your problem is unrelated
> to what I suggested.
I think Myles was right, there is a i2c mux in this server that somehow
multiplexes DIMM devices on the i2c bus. I was able to guess which i2c
ports contain the DIMM info, and which port is the mux, then added the
mux to devicetree.cb and the DIMM ports under it. Now I'm able to use
memory from both CPU's, at least for the combination of DIMM's I have
(2x2x1GB and 2x2x512MB).
So I'm basically able to use these servers now. I would love to have
ACPI and Cool'nQuiet of course, perhaps I'll try to do that later.
Thanks very much for all help! If you want me to commit the new
mainboard to your svn repository let me know.
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