[coreboot] [commit] r6178 - in trunk/src/southbridge/amd: sb600 sb700

[repository service]

Author: zbao
Date: Tue Dec 14 02:47:18 2010
New Revision: 6178
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6178

Log:
Set the ROMSIZE as 4MB.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified:
   trunk/src/southbridge/amd/sb600/Kconfig
   trunk/src/southbridge/amd/sb700/Kconfig
   trunk/src/southbridge/amd/sb700/bootblock.c

Modified: trunk/src/southbridge/amd/sb600/Kconfig
==============================================================================
--- trunk/src/southbridge/amd/sb600/Kconfig	Mon Dec 13 23:16:45 2010	(r6177)
+++ trunk/src/southbridge/amd/sb600/Kconfig	Tue Dec 14 02:47:18 2010	(r6178)
@@ -23,6 +23,11 @@
 	select HAVE_USBDEBUG
 	select TINY_BOOTBLOCK
 
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/amd/sb600/bootblock.c"
+	depends on SOUTHBRIDGE_AMD_SB600
+
 config EHCI_BAR
 	hex
 	default 0xfef00000 if SOUTHBRIDGE_AMD_SB600

Modified: trunk/src/southbridge/amd/sb700/Kconfig
==============================================================================
--- trunk/src/southbridge/amd/sb700/Kconfig	Mon Dec 13 23:16:45 2010	(r6177)
+++ trunk/src/southbridge/amd/sb700/Kconfig	Tue Dec 14 02:47:18 2010	(r6178)
@@ -23,6 +23,11 @@
 	select HAVE_USBDEBUG
 	select TINY_BOOTBLOCK
 
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/amd/sb700/bootblock.c"
+	depends on SOUTHBRIDGE_AMD_SB700
+
 config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
 	bool
 	default n

Modified: trunk/src/southbridge/amd/sb700/bootblock.c
==============================================================================
--- trunk/src/southbridge/amd/sb700/bootblock.c	Mon Dec 13 23:16:45 2010	(r6177)
+++ trunk/src/southbridge/amd/sb700/bootblock.c	Tue Dec 14 02:47:18 2010	(r6178)
@@ -23,12 +23,12 @@
 #include <device/pci_ids.h>
 
 /*
- * Enable 1MB (LPC) ROM access at 0xFFF00000 - 0xFFFFFFFF.
+ * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
  *
  * Hardware should enable LPC ROM by pin straps. This function does not
  * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
  *
- * The SB700 power-on default is to map 256K ROM space.
+ * The SB700 power-on default is to map 512K ROM space.
  *
  * Details: AMD SB700/710/750 BIOS Developer's Guide (BDG), Rev. 1.00,
  *          PN 43366_sb7xx_bdg_pub_1.00, June 2009, section 3.1, page 14.
@@ -39,7 +39,7 @@
 	device_t dev;
 
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
-				PCI_DEVICE_ID_ATI_SB700_LPC), 0);
+				       PCI_DEVICE_ID_ATI_SB700_LPC), 0);
 
 	/* Decode variable LPC ROM address ranges 1 and 2. */
 	reg8 = pci_read_config8(dev, 0x48);
@@ -57,8 +57,10 @@
 	 * Enable LPC ROM range start at:
 	 * 0xfff8(0000): 512KB
 	 * 0xfff0(0000): 1MB
+	 * 0xffe0(0000): 2MB
+	 * 0xffc0(0000): 4MB
 	 */
-	pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */
+	pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
 	/* Enable LPC ROM range end at 0xffff(ffff). */
 	pci_write_config16(dev, 0x6e, 0xffff);
 }