[coreboot] question about post_cache_as_ram() function
namedylan at gmail.com
Fri Dec 17 23:18:38 CET 2010
> DCACHE_RAM_BASE is the start address of the memory addresses that are used for
> DCACHE_RAM_SIZE is the size of that region.
I checked the value from Kconfig under /mainboard/asus/m2v-mx_se/
DCACHE_RAM_BASE is 0xcc000
DCACHE_RAM_SIZE is 0x4000
Why does they set to these value? Does them change?
Do they setup by hardware?
> RAMTOP is the highest address of the memory region that coreboot will use in
>> In addition, why do we need to set new esp here?
>> /* set new esp */ /* before CONFIG_RAMBASE */
>> "subl %0, %%esp\n\t"
>> ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)-
>> (CONFIG_RAMTOP) )
> This moves the stack from CAR area to RAM.
> While in CAR, the stack is laid out at the top end of CAR, growing downwards
> (ie. starting at DCACHE_RAM_BASE + DCACHE_RAM_SIZE).
> While in RAM, it starts at the top end of the ram area used for coreboot
> Before that line the stack is copied from CAR to RAM, then esp is setup so it
> points to the same place in RAM that it pointed to in CAR (that's why we use
> sub, not mov).
i see the copying from CAR to RAM. but I still confused about the value
of esp. Why is this euqation:
esp = esp - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)-
I thought the esp should be: CONFIG_RAMTOP - CONFIG_DCACHE_RAM_SIZE
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