[coreboot] [PATCH] RFC AMD powernow generation for pre fam 0fh
r.marek at assembler.cz
Sat Dec 25 20:08:39 CET 2010
This is RFC patch. It adds support for automatic PSS object generation for AMD
pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite
during one particularly boring flight. Too pity it is only for Opteron CPUs.
Someone needs to finish the second PDF for All others Athlons and Semprons.
It just adds the table to same place where is the fam0fh generator. To make the
powernow work on my Asrock 939 board I had to enable undocumented bit1 in
PM_Misc 67h of SB710. It looks like this bit is documented in SB600 and it is
doing LDT_STOP toggle for C states (and for FID/VID). I remember I had to fix
this toggle for VIA chipset too. It took me some time to figure it out. It
helped that it started to work if the orig bios was booted and halted to S5.
All search was to find out what register was not updated by coreboot).
Whom to ask to fix the AMD documentation?
It is unknown if the bit is necessary for fam 0fh or fam10h, question is if the
second bit CC_en which says: "C State enable. This bit must be set in order to
exercise the C state" should be enabled (it is for me with orig BIOS).
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