[coreboot] [PATCH 4/6] Geode GX2 cleanup patch
peter at stuge.se
Sun Dec 26 06:08:36 CET 2010
> Remove wrong GX2 processor IIOC mode setting on CS5535 southbridge
> code and fix CIS mode comments.
Hm, please talk a little about this?
> +++ src/southbridge/amd/cs5535/early_setup.c (working copy)
> @@ -107,15 +107,11 @@
> - //Only do this if we are building for 5535
> - msr.lo = 0x2;
> - msr.hi = 0x0;
> - wrmsr(VIP_GIO_MSR_SEL, msr);
This code is not added to another place by this patch. Is it simply
completely bogus, but harmless, for 5535? And harmful for GX2? Please
explain a little?
> +++ src/include/cpu/amd/gx2def.h (working copy)
> +#define FG_GIO_MSR_SEL (MSR_FG + 0x2010)
> -#define VIP_GIO_MSR_SEL (MSR_VIP + 0x2010)
(Why remove this?)
> +++ src/cpu/amd/model_gx2/cpureginit.c (working copy)
> - msrnum = MSR_FG + 0x10;
> + msrnum = FG_GIO_MSR_SEL;
This is not the same MSR. Please explain? FG_GIO_MSR_SEL is defined
to MSR_FG + 0x2010 above, so this particular change changes which MSR
is being accessed. Is on purpose?
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