[coreboot] Partial 440BX RAM init by SPD - for the adventurous only!

[Keith Hui]

Hello,

This patch reads SPD data and sets the DRB registers so it no longer hard
code for 64MB in bank 0. Theoretically I can stick three 256MB sticks and
it'll read 768MB.

I referred to both the SPD spec and 440BX datasheet when I wrote this, but
it's too late at night in Toronto so testing will have to wait :-).

As such this is for the highly adventurous to see and I don't expect this to
be committed just yet.

Also a question related to this: How can I get romcc to provide me an
assembly listing of a C file compiled? I want to see the assembly code that
compiling this generates.

Anyway, I got tired of trying to trace the vendor BIOS I have and just coded
this up from spec from scratch, so this should legally be safe, and thus...

Signed-off-by: Keith Hui <buurin at gmail.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20100223/37a96d3b/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 440bxraminit.patch
Type: application/octet-stream
Size: 5052 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20100223/37a96d3b/attachment.obj>