[coreboot] Integrated graphics controller on second bus?

Sun Jan 3 15:22:15 CET 2010

Peter Stuge wrote:
> Andrej Skirn wrote:
>   
>> So how do I define a device on second PCI bus for CoreBoot?
>>     
>
> It should be discovered automatically.
>   

Thanks for the reply. I'm probably missing something really elementary, 
but still can't get CoreBoot to locate and enable the video device. Even 
considered trying to run the VGA BIOS cold without enabling the device 
in vain hope it would know how to enable it, but calling 
cbfs_and_run_core() from hardwaremain requires at the least more build 
script wizardry than I can yet figure out. Here's some details in case 
somebody can offer leads on what's wrong. The CLE266 datasheet appears 
to be currently available at 
http://www.datasheetarchive.com/CLE266-datasheet.html in case anybody's 
interested, though I'd expect the problem to be more with standard PCI 
setup. It's basically using EPIA-M code from the svn head for all of 
this Northbridge related code.

I've set up the relation in devicetree with:
                device pci 1.0 on # AGP
                        device pci 0.0 on end # VGA
                end
In practice this does nothing, of course, but does let me see bit more 
debug output about what goes wrong (I have cut out repetitive "bad id" 
rows):

scan_static_bus for Root Device
In vt8623 enable_dev for device APIC_CLUSTER: 0.
APIC_CLUSTER: 0 enabled
In vt8623 enable_dev for device PCI_DOMAIN: 0000.
Finding PCI configuration type.
PCI: Using configuration type 1
POST: 0x5f
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
malloc Enter, size 1092, free_mem_ptr 00030000
malloc 00030000
PCI: 00:00.0 [1106/3123] ops
PCI: 00:00.0 [1106/3123] enabled
In vt8623 enable_dev for device PCI: 00:01.0.
PCI: 00:01.0 [1106/b091] bus ops
PCI: 00:01.0 [1106/b091] enabled
PCI: 00:02.0, bad id 0xffffffff
...
PCI: 00:0e.0, bad id 0xffffffff
PCI: 00:0f.0 [1106/3149] ops
PCI: 00:0f.0 [1106/3149] enabled
PCI: 00:0f.1 [1106/0571] ops
PCI: 00:0f.1 [1106/0571] enabled
PCI: 00:0f.2, bad id 0xffffffff
...
PCI: 00:0f.7, bad id 0xffffffff
PCI: 00:10.0 [1106/3038] ops
PCI: 00:10.0 [1106/3038] enabled
PCI: 00:10.1 [1106/3038] ops
PCI: 00:10.1 [1106/3038] enabled
PCI: 00:10.2 [1106/3038] ops
PCI: 00:10.2 [1106/3038] enabled
PCI: 00:10.3 [1106/3038] ops
PCI: 00:10.3 [1106/3038] enabled
PCI: 00:10.4 [1106/3104] ops
PCI: 00:10.4 [1106/3104] enabled
PCI: 00:10.5 [1106/d104] disabled
PCI: 00:10.6, bad id 0xffffffff
PCI: 00:10.7, bad id 0xffffffff
PCI: 00:11.0 [1106/3227] bus ops
PCI: 00:11.0 [1106/3227] enabled
PCI: 00:11.1, bad id 0xffffffff
...
PCI: 00:11.7, bad id 0xffffffff
PCI: 00:12.0 [1106/3065] ops
PCI: 00:12.0 [1106/3065] disabled
PCI: 00:12.1, bad id 0xffffffff
...
PCI: 00:1f.0, bad id 0xffffffff
POST: 0x25
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
POST: 0x24
In vt8623 enable_dev for device PCI: 01:00.0.
Disabling static device: PCI: 01:00.0
PCI: 01:00.1, bad id 0xffffffff
...
PCI: 01:1f.0, bad id 0xffffffff
POST: 0x25
PCI: pci_scan_bus returning with max=001
POST: 0x55
do_pci_scan_bridge returns max 1

Trying to force the graphics device enable regardless:
In vt8623 enable_dev for device PCI: 01:00.0.
PCI: 01:00.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring.
PCI: 01:00.0 [ffff/ffff] enabled No operations

Apparently all the device registers read as ffh, this could mean the 
bridge is not set-up correctly, so I hard-coded the secondary & 
subordinate bus numbers to 1 in auto.c and the actual Northbridge code 
(some of the EPIA seems to do this anyway), but this changed nothing:
        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, 
PCI_DEVICE_ID_VIA_8633_1), 0);
        if (dev == PCI_DEV_INVALID)
                die("AGP Bridge Not Found\n");
        pci_write_config16(dev, 0x4, 0x0007);
        /* Secondary Bus Number */
        pci_write_config8(dev, 0x19, 0x01);
        /* Subordinate Bus Number */
        pci_write_config8(dev, 0x1a, 0x01);

Dump of non-zero AGP Bridge registers at end of auto.c (epia-m + custom 
code):
00:06 11 91 b0 07 00 30 02 00 00 04 06 00 00 01 00
10:00 00 00 00 00 00 00 00 00 01 01 00 f0 00 00 00
20:00 dc f0 dd 00 d8 f0 db 00 00 00 00 00 00 00 00
30:00 00 00 00 80 00 00 00 00 00 00 00 00 00 0c 00
40:00 08 00 22 20 72 00 00 00 00 00 00 00 00 00 00
80:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00

Dump of AGP Bridge registers in SeaBIOS 0.4.2:
00: 6 11 91 b0 7 0 30 22 0 0 4 6 0 0 1 0
10: 0 0 0 0 0 0 0 0 0 1 1 0 f0 0 0 0
20: 0 fb f0 fc 0 f4 f0 f7 0 0 0 0 0 0 0 0
30: 0 0 0 0 80 0 0 0 0 0 0 0 0 0 c 0
40: 83 45 0 44 24 72 0 0 0 0 0 0 0 0 0 0
80: 1 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0

(I'm not concerned with most of the registers at this point, as the VGA 
BIOS and operating system should be setting a number of them)

Dump of the same from running system with factory BIOS and Windows XP:
 Bus 0 (PCI), Device Number 1, Device Function 0
 Vendor 1106h VIA Technologies Inc
 Device B091h VT8633 Apollo Pro 266 CPU to AGP Controller
 Command 0007h (I/O Access, Memory Access, BusMaster)
 Status A230h (Has Capabilities List, Supports 66MHz, Received Master 
Abort, Detected Parity Error, Medium Timing)
 Revision 00h, Header Type 01h, Bus Latency Timer 00h
 Self test 00h (Self test not supported)
 PCI Class Bridge, type PCI to PCI
 PCI Bridge Information:
   Primary Bus Number 0, Secondary Bus Number 1, Subordinate Bus Number 1
   Secondary Bus Command 000Ch (ISA mapping, VGA mapping)
   Secondary Bus Status 0000h
   Secondary Bus Latency 00h
   I/O Port Range Passed to Secondary Bus : None
   Memory   Range Passed to Secondary Bus : DC000000h to DDFFFFFFh
   Prefetchable Memory Range Passed to Secondary Bus : D8000000h to 
DBFFFFFFh
 New Capabilities List Present:
   Power Management Capability, Version 1.1
     Supports low power State D1
     Does not support PME# signalling
     Current Power State : D0 (Device operational, no power saving)

 Hex-Dump of device configuration space follows:
  0000  06 11 91 B0 07 00 30 A2 00 00 04 06 00 00 01 00
  0010  00 00 00 00 00 00 00 00 00 01 01 00 F0 00 00 00
  0020  00 DC F0 DD 00 D8 F0 DB 00 00 00 00 00 00 00 00
  0030  00 00 00 00 80 00 00 00 00 00 00 00 00 00 0C 00
  0040  83 C5 00 44 24 72 00 00 00 00 00 00 00 00 00 00
  0080  01 00 02 02 00 00 00 00 00 00 00 00 00 00 00 00

>> The Wiki still talks about concatenating the VGA BIOS to the image,
>> although the current way seems to be to include it in CBFS.
>>     
>
> Indeed so.
>
> Are you using Kconfig or the old method with buildtarget?
>
> With Kconfig the way to do it is to select if and how to run the VGA
> BIOS (which x86 emulator to use, or if to run in real mode) and
> provide the filename.
>   
I added the target into Kconfig and set up the options/files in 
menuconfig. The VGA BIOS is added into CBFS with correct vendor & device 
id's, but it's not getting called because the video device behind the 
AGP bridge isn't getting found, either by CoreBoot or SeaBios. I'd run 
it manually just in case it knows how to enable itself, but can't figure 
how to do that correctly.