[coreboot] [commit] r5000 - in trunk/src: arch/i386 cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/sc520 mainboard/emulation/qemu-x86 mainboard/supermicro/h8dmr_fam10 mainboard/tyan/s2912_fam10 southbridge/nvidia/mcp55 southbridge/via/k8t890
svn at coreboot.org
svn at coreboot.org
Wed Jan 6 10:14:08 CET 2010
Author: oxygene
Date: 2010-01-06 10:14:08 +0100 (Wed, 06 Jan 2010)
New Revision: 5000
Modified:
trunk/src/arch/i386/Makefile.tinybootblock.inc
trunk/src/cpu/amd/model_10xxx/Kconfig
trunk/src/cpu/amd/model_fxx/Kconfig
trunk/src/cpu/amd/sc520/Kconfig
trunk/src/mainboard/emulation/qemu-x86/Kconfig
trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
trunk/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc
trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
trunk/src/mainboard/tyan/s2912_fam10/Kconfig
trunk/src/mainboard/tyan/s2912_fam10/Makefile.inc
trunk/src/southbridge/nvidia/mcp55/Makefile.inc
trunk/src/southbridge/via/k8t890/Makefile.inc
Log:
Kconfig builds all boards now.
This patch also aligns the configuration of a couple of
boards more closely to what newconfig does.
Also, the romstrap inc/lds files are declared in the
Makefiles of the southbridges they belong to, instead of
some global file.
AMD CPUs have their own timer functions, so disable UDELAY_IO
for them and set HAVE_INIT_TIMER as appropriate, same for
emulation/qemu-x86.
Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Myles Watson <mylesgw at gmail.com>
Modified: trunk/src/arch/i386/Makefile.tinybootblock.inc
===================================================================
--- trunk/src/arch/i386/Makefile.tinybootblock.inc 2010-01-05 17:35:44 UTC (rev 4999)
+++ trunk/src/arch/i386/Makefile.tinybootblock.inc 2010-01-06 09:14:08 UTC (rev 5000)
@@ -24,20 +24,15 @@
bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds
bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds
bootblock_lds += $(src)/arch/i386/lib/id.lds
-ifeq ($(CONFIG_SOUTHBRIDGE_VIA_K8T890),y)
-bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.lds
-endif
+bootblock_lds += $(chipset_bootblock_lds)
bootblock_inc := $(src)/arch/i386/init/bootblock_prologue.c
bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc
bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc
bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc
bootblock_inc += $(src)/arch/i386/lib/id.inc
+bootblock_inc += $(chipset_bootblock_inc)
-ifeq ($(CONFIG_SOUTHBRIDGE_VIA_K8T890),y)
-bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
-endif
-
ifeq ($(CONFIG_SSE),y)
bootblock_inc += $(src)/cpu/x86/sse_enable.inc
endif
Modified: trunk/src/cpu/amd/model_10xxx/Kconfig
===================================================================
--- trunk/src/cpu/amd/model_10xxx/Kconfig 2010-01-05 17:35:44 UTC (rev 4999)
+++ trunk/src/cpu/amd/model_10xxx/Kconfig 2010-01-06 09:14:08 UTC (rev 5000)
@@ -4,6 +4,7 @@
select USE_PRINTK_IN_CAR
select USE_DCACHE_RAM
select SSE
+ select HAVE_INIT_TIMER
config CPU_ADDR_BITS
int
@@ -25,3 +26,7 @@
default 0x04000
depends on CPU_AMD_MODEL_10XXX
+config UDELAY_IO
+ bool
+ default n
+ depends on CPU_AMD_MODEL_10XXX
Modified: trunk/src/cpu/amd/model_fxx/Kconfig
===================================================================
--- trunk/src/cpu/amd/model_fxx/Kconfig 2010-01-05 17:35:44 UTC (rev 4999)
+++ trunk/src/cpu/amd/model_fxx/Kconfig 2010-01-06 09:14:08 UTC (rev 5000)
@@ -4,6 +4,7 @@
select USE_PRINTK_IN_CAR
select USE_DCACHE_RAM
select SSE
+ select HAVE_INIT_TIMER
config CPU_ADDR_BITS
int
@@ -25,3 +26,8 @@
default 0x01000
depends on CPU_AMD_MODEL_FXX
+
+config UDELAY_IO
+ bool
+ default n
+ depends on CPU_AMD_MODEL_FXX
Modified: trunk/src/cpu/amd/sc520/Kconfig
===================================================================
--- trunk/src/cpu/amd/sc520/Kconfig 2010-01-05 17:35:44 UTC (rev 4999)
+++ trunk/src/cpu/amd/sc520/Kconfig 2010-01-06 09:14:08 UTC (rev 5000)
@@ -1,3 +1,8 @@
config CPU_AMD_SC520
bool
+config UDELAY_IO
+ bool
+ default n
+ depends on CPU_AMD_SC520
+
Modified: trunk/src/mainboard/emulation/qemu-x86/Kconfig
===================================================================
--- trunk/src/mainboard/emulation/qemu-x86/Kconfig 2010-01-05 17:35:44 UTC (rev 4999)
+++ trunk/src/mainboard/emulation/qemu-x86/Kconfig 2010-01-06 09:14:08 UTC (rev 5000)
@@ -27,3 +27,8 @@
bool
default n
depends on BOARD_EMULATION_QEMU_X86
+
+config UDELAY_IO
+ bool
+ default n
+ depends on BOARD_EMULATION_QEMU_X86
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig 2010-01-05 17:35:44 UTC (rev 4999)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig 2010-01-06 09:14:08 UTC (rev 5000)
@@ -15,6 +15,8 @@
select LIFT_BSP_APIC_ID
select AMDMCT
select BOARD_ROMSIZE_KB_1024
+ select TINY_BOOTBLOCK
+ select ENABLE_APIC_EXT_ID
config MAINBOARD_DIR
string
@@ -23,27 +25,42 @@
config DCACHE_RAM_BASE
hex
- default 0xc8000
+ default 0xc4000
depends on BOARD_SUPERMICRO_H8DMR_FAM10
config DCACHE_RAM_SIZE
hex
- default 0x08000
+ default 0x0c000
depends on BOARD_SUPERMICRO_H8DMR_FAM10
config DCACHE_RAM_GLOBAL_VAR_SIZE
hex
- default 0x01000
+ default 0x04000
depends on BOARD_SUPERMICRO_H8DMR_FAM10
+config RAMBASE
+ hex
+ default 0x200000
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config RAMTOP
+ hex
+ default 0x1000000
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config HEAP_SIZE
+ hex
+ default 0xc0000
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
config APIC_ID_OFFSET
hex
- default 0x10
+ default 0x0
depends on BOARD_SUPERMICRO_H8DMR_FAM10
config MEM_TRAIN_SEQ
int
- default 1
+ default 2
depends on BOARD_SUPERMICRO_H8DMR_FAM10
config SB_HT_CHAIN_ON_BUS0
@@ -78,7 +95,7 @@
config MAX_CPUS
int
- default 4
+ default 8
depends on BOARD_SUPERMICRO_H8DMR_FAM10
config MAX_PHYSICAL_CPUS
@@ -88,12 +105,12 @@
config HT_CHAIN_END_UNITID_BASE
hex
- default 0x0
+ default 0x20
depends on BOARD_SUPERMICRO_H8DMR_FAM10
config HT_CHAIN_UNITID_BASE
hex
- default 0x0
+ default 0x1
depends on BOARD_SUPERMICRO_H8DMR_FAM10
config USE_INIT
@@ -115,3 +132,8 @@
string
default "mc_patch_0100009f.h"
depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config SERIAL_CPU_INIT
+ bool
+ default n
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc 2010-01-05 17:35:44 UTC (rev 4999)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc 2010-01-06 09:14:08 UTC (rev 5000)
@@ -30,19 +30,12 @@
initobj-y += crt0.o
# FIXME in $(top)/Makefile
-crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
-crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/arch/i386/lib/id.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
crt0-y += auto.inc
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
-ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
-ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/arch/i386/lib/id.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
+ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
ifdef POST_EVALUATION
@@ -55,19 +48,19 @@
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
- iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
- mv pci2.hex ssdt2.c
+ iasl -p $(obj)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
+ perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' $(obj)/pci2.hex
+ mv $(obj)/pci2.hex $(obj)/ssdt2.c
$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
- iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
- perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
- mv pci3.hex ssdt3.c
+ iasl -p $(obj)/pci3 -tc $(CONFIG_MAINBOARD)/
+ perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' $(obj)/pci3.hex
+ mv $(obj)/pci3.hex $(obj)/ssdt3.c
$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
- iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
- mv pci4.hex ssdt4.c
+ iasl -p $(obj)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
+ perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' $(obj)/pci4.hex
+ mv $(obj)/pci4.hex $(obj)/ssdt4.c
$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb 2010-01-05 17:35:44 UTC (rev 4999)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb 2010-01-06 09:14:08 UTC (rev 5000)
@@ -1,5 +1,3 @@
-dir /southbridge/nvidia/mcp55
-
chip northbridge/amd/amdfam10/root_complex
device apic_cluster 0 on
chip cpu/amd/socket_F_1207
Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig
===================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/Kconfig 2010-01-05 17:35:44 UTC (rev 4999)
+++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig 2010-01-06 09:14:08 UTC (rev 5000)
@@ -13,10 +13,10 @@
select HAVE_HARD_RESET
select IOAPIC
select LIFT_BSP_APIC_ID
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select BOARD_ROMSIZE_KB_1024
select ENABLE_APIC_EXT_ID
select AMDMCT
+ select TINY_BOOTBLOCK
config MAINBOARD_DIR
string
@@ -25,22 +25,22 @@
config DCACHE_RAM_BASE
hex
- default 0xc8000
+ default 0xc4000
depends on BOARD_TYAN_S2912_FAM10
config DCACHE_RAM_SIZE
hex
- default 0x08000
+ default 0x0c000
depends on BOARD_TYAN_S2912_FAM10
config DCACHE_RAM_GLOBAL_VAR_SIZE
hex
- default 0x01000
+ default 0x04000
depends on BOARD_TYAN_S2912_FAM10
config APIC_ID_OFFSET
hex
- default 16
+ default 0
depends on BOARD_TYAN_S2912_FAM10
config MEM_TRAIN_SEQ
@@ -95,12 +95,12 @@
config MAX_CPUS
int
- default 2
+ default 8
depends on BOARD_TYAN_S2912_FAM10
config MAX_PHYSICAL_CPUS
int
- default 1
+ default 2
depends on BOARD_TYAN_S2912_FAM10
config HW_MEM_HOLE_SIZE_AUTO_INC
@@ -110,12 +110,12 @@
config HT_CHAIN_UNITID_BASE
hex
- default 0x0
+ default 0x1
depends on BOARD_TYAN_S2912_FAM10
config HT_CHAIN_END_UNITID_BASE
hex
- default 0x0
+ default 0x20
depends on BOARD_TYAN_S2912_FAM10
config USE_INIT
@@ -148,3 +148,27 @@
default "mc_patch_01000095.h"
depends on BOARD_TYAN_S2912_FAM10
+config SERIAL_CPU_INIT
+ bool
+ default n
+ depends on BOARD_TYAN_S2912_FAM10
+
+config ACPI_SSDTX_NUM
+ hex
+ default 0x1f
+ depends on BOARD_TYAN_S2912_FAM10
+
+config RAMBASE
+ hex
+ default 0x200000
+ depends on BOARD_TYAN_S2912_FAM10
+
+config RAMTOP
+ hex
+ default 0x1000000
+ depends on BOARD_TYAN_S2912_FAM10
+
+config HEAP_SIZE
+ hex
+ default 0xc0000
+ depends on BOARD_TYAN_S2912_FAM10
Modified: trunk/src/mainboard/tyan/s2912_fam10/Makefile.inc
===================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/Makefile.inc 2010-01-05 17:35:44 UTC (rev 4999)
+++ trunk/src/mainboard/tyan/s2912_fam10/Makefile.inc 2010-01-06 09:14:08 UTC (rev 5000)
@@ -30,19 +30,12 @@
# This is part of the conversion to init-obj and away from included code.
initobj-y += crt0.o
-crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
-crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/arch/i386/lib/id.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
crt0-y += auto.inc
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
-ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
-ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/arch/i386/lib/id.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
+ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
Modified: trunk/src/southbridge/nvidia/mcp55/Makefile.inc
===================================================================
--- trunk/src/southbridge/nvidia/mcp55/Makefile.inc 2010-01-05 17:35:44 UTC (rev 4999)
+++ trunk/src/southbridge/nvidia/mcp55/Makefile.inc 2010-01-06 09:14:08 UTC (rev 5000)
@@ -14,3 +14,6 @@
driver-$(CONFIG_GENERATE_ACPI_TABLES) += mcp55_fadt.o
obj-y += mcp55_reset.o
+
+chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
+chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds
Modified: trunk/src/southbridge/via/k8t890/Makefile.inc
===================================================================
--- trunk/src/southbridge/via/k8t890/Makefile.inc 2010-01-05 17:35:44 UTC (rev 4999)
+++ trunk/src/southbridge/via/k8t890/Makefile.inc 2010-01-06 09:14:08 UTC (rev 5000)
@@ -7,3 +7,6 @@
driver-y += k8t890_traf_ctrl.o
driver-y += k8t890_error.o
driver-y += k8m890_chrome.o
+
+chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
+chipset_bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.lds
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