[coreboot] coreboot and MSM800BEV

Piotr Piwko piotr.piwko at gmail.com
Thu Jan 7 14:22:13 CET 2010


Hello,

I am preparing the coreboot version for MSM800BEV board from Digital
Logic. This is the same branch as MSM800SEV board so, I've decided
that is a good starting point.

So, I built and loaded it to my flash memory and finally run.
Unfortunately, it stops at "Uncompressing coreboot to ram" message.
I've found that it hangs on calling the 'cbfs_and_run_core' function
which is in 'cpu/amd/model_lx/cache_as_ram.inc' file.

Is it a known issue? Maybe you can give my any hints to fix this situation?

Thank you in advance for your engagement.

PS. I have attached the log from my serial port

-- 
Piotr Piwko
http://www.embedded-engineering.pl/
-------------- next part --------------
coreboot-2.0.0-r4949M.0Fallback czw, 7 sty 2010, 12:55:27 CET starting...
_MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000392:0000180c
Configuring PLL


coreboot-2.0.0-r4949M.0Fallback czw, 7 sty 2010, 12:55:27 CET starting...
_MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000392:07de000c
Done pll_reset
Castle 2.0 BTM periodic sync period.
Enable Quack for fewer re-RAS on the MC
 GLIU port active enable
Set the Delay Control in GLCP
SMBUS READ ERROR:03 device:a2
Try to write GLCP_DELAY_CONTROLS: hi 83f100aa and lo 56960004
SetDelayControl done
Enable RSDC
FPU imprecise exceptions bit
Enable Suspend on HLT & PAUSE instructions
Enable SUSP and allow TSC to run in Suspend
Setup throttling delays to proper mode
Done cpuRegInit
Ram1.00
Ram2.00
===========================sdram_set_spd_register
======================================
===========================Check DIMM 0======================================
===========================Check DIMM 1======================================
SMBUS READ ERROR:03 device:a2
===========================Check DDR MAX======================================
SMBUS READ ERROR:03 device:a2
===========================AUTOSIZE DIMM 0======================================
===========================Check present======================================
===========================MODBANKS======================================
===========================FIELDBANKS======================================
===========================SPDNUMROWS======================================
===========================SPDBANKDENSITY======================================
===========================DIMMSIZE======================================
===========================BEFORT CTZ======================================
===========================TEST DIMM SIZE>8=====================================
===========================PAGESIZE======================================
===========================MAXCOLADDR======================================
===========================>12address test======================================
===========================RDMSR CF07======================================
===========================WRMSR CF07======================================
===========================ALL DONE======================================
===========================AUTOSIZE DIMM 1======================================
===========================Check present======================================
SMBUS READ ERROR:03 device:a2
===========================set cas latency======================================
SMBUS READ ERROR:03 device:a2
===========================set all latency======================================
SMBUS READ ERROR:03 device:a2
SMBUS READ ERROR:03 device:a2
SMBUS READ ERROR:03 device:a2
SMBUS READ ERROR:03 device:a2
SMBUS READ ERROR:03 device:a2
===========================set emrs======================================
SMBUS READ ERROR:03 device:a2
===========================set ref rate======================================
SMBUS READ ERROR:03 device:a2
Ram3
DRAM controller init done.
RAM DLL lock
Ram4
Testing DRAM : 00000000 - 000a0000
DRAM fill: 0x00000000-0x000a0000
000a0000 
DRAM filled
DRAM verify: 0x00000000-0x000a0000
000a0000 
DRAM range verified.
Done.
POST 02
Past wbinvd
Uncompressing coreboot to ram.


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