[coreboot] Future coreboot phases?

[Peter Stuge]

Rudolf Marek wrote:
> The DQS values are stored in chipset S3 "NVRAM" during first boot,
> and used later when resume to fill them in. It could be done via
> simple backup of all mem cntrl regs but it is not done so.

I think this is a brilliant idea for improvement - it would also
reduce the resume time ever so slightly. Either a structure for the
chipset-specific registers that are needed, filled and saved at first
boot and reused on resume - or a super simple blob copy of all
registers. (If there's enough space?)


//Peter