[coreboot] coreboot and MSM800BEV

[Piotr Piwko]

I've found the way to force the normal boot mode in boot process. I
just set the
RTC_NORMAL_BOOT_FLAG_SET bit in check_normal_boot_flag() function
(patch is attached).

Now the boot process seems to be ok, but it still hangs on the
execution __asm__("wbinvd\n"); in main function of
mainboard/adl/msm800sev/initram.c file ... (please, see attached log).

PS. Let me know if I am too verbose in this thread. I just want to
help future users.

-- 
Piotr Piwko
http://www.embedded-engineering.pl/
-------------- next part --------------
coreboot-3.0.1177 Tue Jan 12 12:24:18 CET 2010 starting... (console_loglevel=8)
Choosing normal boot.
LAR: Attempting to open 'normal/initram/segment0'.
LAR: Start 0xfff00000 len 0x100000
LAR: seen member normal/option_table at 0xfff00000, size 1160
LAR: seen member normal/initram/segment0 at 0xfff004e0, size 6464
LAR: CHECK normal/initram/segment0 @ 0xfff004e0
start 0xfff00530 len 6464 reallen 6464 compression 0 entry 0x00001206 loadaddre0
Entry point is 0xfff01736
pll_reset: read msr 0x4c000014
_MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000392:0000180c
Configuring PLL
Resetting the processor after PLL configuration for the changes to take effect


coreboot-3.0.1177 Tue Jan 12 12:24:18 CET 2010 starting... (console_loglevel=8)
Choosing normal boot.
LAR: Attempting to open 'normal/initram/segment0'.
LAR: Start 0xfff00000 len 0x100000
LAR: seen member normal/option_table at 0xfff00000, size 1160
LAR: seen member normal/initram/segment0 at 0xfff004e0, size 6464
LAR: CHECK normal/initram/segment0 @ 0xfff004e0
start 0xfff00530 len 6464 reallen 6464 compression 0 entry 0x00001206 loadaddre0
Entry point is 0xfff01736
pll_reset: read msr 0x4c000014
_MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000392:07de000c
Done pll_reset
spd_read_byte dev 00a0
 addr 0d returns 08
spd_read_byte dev 00a0
 addr 05 returns 01
spd_read_byte dev 00a0
 addr 0d returns 08
spd_read_byte dev 00a0
 addr 05 returns 01
Done cpubug fixes
spd_read_byte dev 00a0
 addr 15 returns 20
spd_read_byte dev 00a0
 addr 15 returns 20
spd_read_byte dev 00a0
 addr 09 returns 60
spd_read_byte dev 00a0
 addr 09 returns 60
ddr max speed is 333
========== Check present =======================================================
spd_read_byte dev 00a0
 addr 02 returns 07
========== MODBANKS ============================================================
spd_read_byte dev 00a0
 addr 05 returns 01
========== FIELDBANKS ==========================================================
spd_read_byte dev 00a0
 addr 11 returns 04
========== SPDNUMROWS ==========================================================
spd_read_byte dev 00a0
 addr 03 returns 0d
spd_read_byte dev 00a0
 addr 04 returns 0b
========== SPDBANKDENSITY ======================================================
spd_read_byte dev 00a0
 addr 1f returns 80
DIMM size is 80
========== BEFORT CTZ ==========================================================
========== TEST DIMM SIZE>8 ====================================================
========== PAGESIZE ============================================================
spd_read_byte dev 00a0
 addr 04 returns 0b
========== MAXCOLADDR ==========================================================
========== RDMSR CF07 ==========================================================
========== WRMSR CF07 ==========================================================
CF07(20000018): 10071007.00000040
========== ALL DONE ============================================================
========== Check present =======================================================
spd_read_byte dev 00a0
 addr 02 returns 07
========== MODBANKS ============================================================
spd_read_byte dev 00a0
 addr 05 returns 01
========== FIELDBANKS ==========================================================
spd_read_byte dev 00a0
 addr 11 returns 04
========== SPDNUMROWS ==========================================================
spd_read_byte dev 00a0
 addr 03 returns 0d
spd_read_byte dev 00a0
 addr 04 returns 0b
========== SPDBANKDENSITY ======================================================
spd_read_byte dev 00a0
 addr 1f returns 80
DIMM size is 80
========== BEFORT CTZ ==========================================================
========== TEST DIMM SIZE>8 ====================================================
========== PAGESIZE ============================================================
spd_read_byte dev 00a0
 addr 04 returns 0b
========== MAXCOLADDR ==========================================================
========== RDMSR CF07 ==========================================================
========== WRMSR CF07 ==========================================================
CF07(20000018): 10077014.00000040
========== ALL DONE ============================================================
spd_read_byte dev 00a0
 addr 12 returns 0c
spd_read_byte dev 00a0
 addr 17 returns 75
spd_read_byte dev 00a0
 addr 19 returns 00
spd_read_byte dev 00a0
 addr 12 returns 0c
spd_read_byte dev 00a0
 addr 17 returns 75
spd_read_byte dev 00a0
 addr 19 returns 00
Set CAS latency to 2
spd_read_byte dev 00a0
 addr 1e returns 2a
spd_read_byte dev 00a0
 addr 1e returns 2a
spd_read_byte dev 00a0
 addr 1b returns 48
spd_read_byte dev 00a0
 addr 1b returns 48
spd_read_byte dev 00a0
 addr 1d returns 48
spd_read_byte dev 00a0
 addr 1d returns 48
spd_read_byte dev 00a0
 addr 1c returns 30
spd_read_byte dev 00a0
 addr 1c returns 30
spd_read_byte dev 00a0
 addr 2a returns 48
spd_read_byte dev 00a0
 addr 2a returns 48
spd_read_byte dev 00a0
 addr 16 returns c0
spd_read_byte dev 00a0
 addr 16 returns c0
spd_read_byte dev 00a0
 addr 0c returns 82
spd_read_byte dev 00a0
 addr 0c returns 82
Refresh rate set to 7
DRAM controller init done.
RAM DLL lock
12:24:19Jan 12 2010
Before wbinvd
-------------- next part --------------
A non-text attachment was scrubbed...
Name: normal_boot_mode.patch
Type: text/x-diff
Size: 794 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20100112/e119492f/attachment.bin>