[coreboot] The firmware traps in SIS6xx/7xx/96x type chipsets
r.marek at assembler.cz
Tue Jul 6 16:53:50 CEST 2010
>I can not be sure about that because of
>this firmware trap feature of the chipsets I mention. So are those
> firmware traps in the SIS chipsets are effective on the boot process of
> the processor? Or any other reasons?
I think they are independent of CPU itself. It usually configures some registers
in chipsets for default values, like SB-NB bus.
If you cannot see any fetches except those, the CPU is not running or is unable
to talk to the flash (defective route).
The thermtrip is sw independent so does not play role here.
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