[coreboot] 3 questions about coreboot
hagigatali at gmail.com
Wed Jul 7 06:42:42 CEST 2010
My chipset is Intel Core2Due/945/ICH7.
I have 3 questions.
I wonder how PCI memory read cycles can read an instruction from
F000:FFF0 right after reset which is the first instruction of BIOS.
Does Coreboot writes into PCI configuration space of Device 31 of
ICH7-south bridge(LPC controller)? before initializing the
configuration space of Device 0 of 82945(which is memory controller)?
I mean the hardware immediately accesses BIOS chip after reset but at
some point all memory read/write cycles are claimed by 945 and memory
What is the code flow of Coreboot? Where does
it start? and how it contines?
m/acpi we have some asl files.
What language they have been written in? Like superio.asl
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the coreboot