[coreboot] AMD CAR quiz question

Rudolf Marek r.marek at assembler.cz
Sun Jun 6 18:29:01 CEST 2010


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> Afaik it's "ECC clearing" which is implemented several times in the
> tree, including stage2.

Nope, the APs can init the memory controller too. Check
CONFIG_MEM_TRAIN_SEQ 0 for BSP only
1 = train_ram_on_node is called from init_cpus
2 = dunno - looks like it is also done in parallel but I could not find how it
works.

Lot of boards sets it up for 2 a think only one to 1

Thanks,
Rudolf
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