[coreboot] [h8dme-fam10] acquiring coreboot skills from scratch somewhat daunting

Myles Watson mylesgw at gmail.com
Thu Jun 10 16:31:06 CEST 2010


On Thu, Jun 10, 2010 at 7:38 AM, Joe Korty <joe.korty at ccur.com> wrote:
> Hi,
> As a learning experience, I've been trying to port coreboot to the
> supermicro h8dme-2 w/ AMD K10.
Ward and others have tried this board in the past.  There seems to be
something wrong with multi-core setup for K10.

If you search the mailing list for "h8dme fam10", it might give you
some help.  I would disable all the other processors until you get the
board working.

CONFIG_LOGICAL_CPUS 0
CONFIG_SMP 0
CONFIG_MAX_PHYSICAL_CPUS 1

> I started with the h8dmr_fam10 port since the h8dmr is identical, spec-wise,
> to the h8dme except that it has half the number of dimm slots.  Also there
> is both K8 and K10 versions of coreboot for the h8dmr which in principle
> makes the study of the differences a good way to learn coreboot internals.
I agree that's a good approach.  K8 and fam10 code are pretty similar,
though they could be made even more similar.

> In any case I have not been able to find where the info in spd_addr.h comes
> from, so I have not been able to make it correct for my board.  How does one
> construct this table?  In general, how does one construct devicetree.cb and
> the other tables from scratch?
I don't know that anyone does it from scratch.  The idea is to make
the devicetree as minimal as possible.  That usually means including
the processor and configuring the southbridge buses.  The rest can
usually be found.


> Is there an apprenticeship program somewhere, perhaps at some conference?
I don't know.  There have been some talks and short tutorials, but I
haven't heard of an official training program.

> How do people in general get their coreboot skill-set jump-started?
IRC and the mailing list is what I've heard most.  I've used the mailing list.

Qemu and SimNOW are both helpful, too.  SimNOW exhibits the same
problems for fam10 as hardware (super slow initialization and problems
with logical CPUs), so fixing it there would probably help.

Thanks,
Myles




More information about the coreboot mailing list