[coreboot] [commit] r5632 - trunk/util/inteltool
repository service
svn at coreboot.org
Thu Jun 17 00:21:20 CEST 2010
Author: linux_junkie
Date: Thu Jun 17 00:21:19 2010
New Revision: 5632
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5632
Log:
This patch adds inteltool support for i810E and ICH2.
Signed-off-by: Joseph Smith <joe at settoplinux.org>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Modified:
trunk/util/inteltool/gpio.c
trunk/util/inteltool/inteltool.c
trunk/util/inteltool/inteltool.h
trunk/util/inteltool/memory.c
trunk/util/inteltool/pcie.c
trunk/util/inteltool/powermgt.c
trunk/util/inteltool/rootcmplx.c
Modified: trunk/util/inteltool/gpio.c
==============================================================================
--- trunk/util/inteltool/gpio.c Fri Jun 11 16:25:40 2010 (r5631)
+++ trunk/util/inteltool/gpio.c Thu Jun 17 00:21:19 2010 (r5632)
@@ -39,6 +39,25 @@
{ 0x3C, 4, "RESERVED" }
};
+static const io_register_t ich2_gpio_registers[] = {
+ { 0x00, 4, "GPIO_USE_SEL" },
+ { 0x04, 4, "GP_IO_SEL" },
+ { 0x08, 4, "RESERVED" },
+ { 0x0c, 4, "GP_LVL" },
+ { 0x10, 4, "RESERVED" },
+ { 0x14, 4, "GPO_TTL" },
+ { 0x18, 4, "GPO_BLINK" },
+ { 0x1c, 4, "RESERVED" },
+ { 0x20, 4, "RESERVED" },
+ { 0x24, 4, "RESERVED" },
+ { 0x28, 4, "RESERVED" },
+ { 0x2c, 4, "GPI_INV" },
+ { 0x30, 4, "RESERVED" },
+ { 0x34, 4, "RESERVED" },
+ { 0x38, 4, "RESERVED" },
+ { 0x3C, 4, "RESERVED" }
+};
+
static const io_register_t ich4_gpio_registers[] = {
{ 0x00, 4, "GPIO_USE_SEL" },
{ 0x04, 4, "GP_IO_SEL" },
@@ -176,6 +195,11 @@
gpio_registers = ich4_gpio_registers;
size = ARRAY_SIZE(ich4_gpio_registers);
break;
+ case PCI_DEVICE_ID_INTEL_ICH2:
+ gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
+ gpio_registers = ich2_gpio_registers;
+ size = ARRAY_SIZE(ich2_gpio_registers);
+ break;
case PCI_DEVICE_ID_INTEL_ICH:
case PCI_DEVICE_ID_INTEL_ICH0:
gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
Modified: trunk/util/inteltool/inteltool.c
==============================================================================
--- trunk/util/inteltool/inteltool.c Fri Jun 11 16:25:40 2010 (r5631)
+++ trunk/util/inteltool/inteltool.c Thu Jun 17 00:21:19 2010 (r5632)
@@ -34,6 +34,7 @@
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, "i810E DC-133" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" },
Modified: trunk/util/inteltool/inteltool.h
==============================================================================
--- trunk/util/inteltool/inteltool.h Fri Jun 11 16:25:40 2010 (r5631)
+++ trunk/util/inteltool/inteltool.h Thu Jun 17 00:21:19 2010 (r5632)
@@ -55,6 +55,7 @@
#define PCI_DEVICE_ID_INTEL_82810 0x7120
#define PCI_DEVICE_ID_INTEL_82810DC 0x7122
+#define PCI_DEVICE_ID_INTEL_82810E_MC 0x7124
#define PCI_DEVICE_ID_INTEL_82830M 0x3575
#define PCI_DEVICE_ID_INTEL_82845 0x1a30
#define PCI_DEVICE_ID_INTEL_82915 0x2580
Modified: trunk/util/inteltool/memory.c
==============================================================================
--- trunk/util/inteltool/memory.c Fri Jun 11 16:25:40 2010 (r5631)
+++ trunk/util/inteltool/memory.c Thu Jun 17 00:21:19 2010 (r5632)
@@ -50,6 +50,7 @@
case PCI_DEVICE_ID_INTEL_82443LX:
case PCI_DEVICE_ID_INTEL_82443BX:
case PCI_DEVICE_ID_INTEL_82810:
+ case PCI_DEVICE_ID_INTEL_82810E_MC:
case PCI_DEVICE_ID_INTEL_82810DC:
case PCI_DEVICE_ID_INTEL_82830M:
printf("This northbrigde does not have MCHBAR.\n");
Modified: trunk/util/inteltool/pcie.c
==============================================================================
--- trunk/util/inteltool/pcie.c Fri Jun 11 16:25:40 2010 (r5631)
+++ trunk/util/inteltool/pcie.c Thu Jun 17 00:21:19 2010 (r5632)
@@ -49,6 +49,7 @@
break;
case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810DC:
+ case PCI_DEVICE_ID_INTEL_82810E_MC:
case PCI_DEVICE_ID_INTEL_82830M:
printf("This northbrigde does not have EPBAR.\n");
return 1;
@@ -102,6 +103,7 @@
break;
case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810DC:
+ case PCI_DEVICE_ID_INTEL_82810E_MC:
printf("This northbrigde does not have DMIBAR.\n");
return 1;
default:
@@ -156,6 +158,7 @@
break;
case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810DC:
+ case PCI_DEVICE_ID_INTEL_82810E_MC:
printf("Error: This northbrigde does not have PCIEXBAR.\n");
return 1;
default:
Modified: trunk/util/inteltool/powermgt.c
==============================================================================
--- trunk/util/inteltool/powermgt.c Fri Jun 11 16:25:40 2010 (r5631)
+++ trunk/util/inteltool/powermgt.c Thu Jun 17 00:21:19 2010 (r5632)
@@ -299,6 +299,69 @@
{ 0x7c, 4, "RESERVED" },
};
+static const io_register_t ich2_pm_registers[] = {
+ { 0x00, 2, "PM1_STS" },
+ { 0x02, 2, "PM1_EN" },
+ { 0x04, 4, "PM1_CNT" },
+ { 0x08, 4, "PM1_TMR" },
+ { 0x0c, 4, "RESERVED" },
+ { 0x10, 4, "PROC_CNT" },
+#if DANGEROUS_REGISTERS
+ /* This register returns 0 on read, but reading it may cause
+ * the system to enter C2 state, which might hang the system.
+ */
+ { 0x14, 1, "LV2" },
+ { 0x15, 1, "RESERVED" },
+ { 0x16, 2, "RESERVED" },
+#endif
+ { 0x18, 4, "RESERVED" },
+ { 0x1c, 4, "RESERVED" },
+ { 0x20, 4, "RESERVED" },
+ { 0x24, 4, "RESERVED" },
+ { 0x28, 2, "GPE0_STS" },
+ { 0x2a, 2, "GPE0_EN" },
+ { 0x2c, 2, "GPE1_STS" },
+ { 0x2e, 2, "GPE1_EN" },
+ { 0x30, 2, "SMI_EN" },
+ { 0x32, 2, "RESERVED" },
+ { 0x34, 2, "SMI_STS" },
+ { 0x36, 2, "RESERVED" },
+ { 0x38, 4, "RESERVED" },
+ { 0x3c, 4, "RESERVED" },
+ { 0x40, 2, "MON_SMI_STS" },
+ { 0x42, 2, "RESERVED" },
+ { 0x44, 2, "DEV_TRP_STS" },
+ { 0x46, 2, "RESERVED" },
+ { 0x48, 2, "TRP_EN" },
+ { 0x4A, 2, "RESERVED" },
+ { 0x4c, 2, "BUS_ADDR_TRACK" },
+ { 0x4e, 1, "BUS_CYC_TRACK" },
+ { 0x4f, 1, "RESERVED" },
+ { 0x50, 4, "RESERVED" },
+ { 0x54, 4, "RESERVED" },
+ { 0x58, 4, "RESERVED" },
+ { 0x5c, 4, "RESERVED" },
+ /* Here start the TCO registers */
+ { 0x60, 1, "TCO_RLD" },
+ { 0x61, 1, "TCO_TMR" },
+ { 0x62, 1, "TCO_DAT_IN" },
+ { 0x63, 1, "TCO_DAT_OUT" },
+ { 0x64, 2, "TCO1_STS" },
+ { 0x66, 2, "TCO2_STS" },
+ { 0x68, 2, "TCO1_CNT" },
+ { 0x6a, 2, "TCO2_CNT" },
+ { 0x6c, 1, "TCO_MESSAGE1" },
+ { 0x6d, 1, "TCO_MESSAGE2" },
+ { 0x6e, 1, "TCO_WDSTATUS" },
+ { 0x6f, 1, "RESERVED" },
+ { 0x70, 1, "SW_IRQ_GEN" },
+ { 0x71, 1, "RESERVED" },
+ { 0x72, 2, "RESERVED" },
+ { 0x74, 4, "RESERVED" },
+ { 0x78, 4, "RESERVED" },
+ { 0x7c, 4, "RESERVED" },
+};
+
static const io_register_t ich0_pm_registers[] = {
{ 0x00, 2, "PM1_STS" },
{ 0x02, 2, "PM1_EN" },
@@ -443,6 +506,11 @@
pm_registers = ich4_pm_registers;
size = ARRAY_SIZE(ich4_pm_registers);
break;
+ case PCI_DEVICE_ID_INTEL_ICH2:
+ pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+ pm_registers = ich2_pm_registers;
+ size = ARRAY_SIZE(ich2_pm_registers);
+ break;
case PCI_DEVICE_ID_INTEL_ICH0:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich0_pm_registers;
Modified: trunk/util/inteltool/rootcmplx.c
==============================================================================
--- trunk/util/inteltool/rootcmplx.c Fri Jun 11 16:25:40 2010 (r5631)
+++ trunk/util/inteltool/rootcmplx.c Thu Jun 17 00:21:19 2010 (r5632)
@@ -47,6 +47,7 @@
break;
case PCI_DEVICE_ID_INTEL_ICH:
case PCI_DEVICE_ID_INTEL_ICH0:
+ case PCI_DEVICE_ID_INTEL_ICH2:
case PCI_DEVICE_ID_INTEL_ICH4:
case PCI_DEVICE_ID_INTEL_ICH4M:
printf("This southbridge does not have RCBA.\n");
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