[coreboot] [PATCH] ASUS P2B-LS support, RAM detection for 440BX, add Slot 1 CPU, Microcode for Intel Tualatin CPUs
mark.marshall at csr.com
Fri Mar 5 14:04:27 CET 2010
Joseph Smith wrote:
> On 03/05/2010 03:03 AM, Mark Marshall wrote:
>> On 04/03/10 13:10, Joseph Smith wrote:
>>> On 03/04/2010 07:38 AM, Joseph Smith wrote:
>>>> On 03/04/2010 07:30 AM, Uwe Hermann wrote:
>>>>> On Thu, Mar 04, 2010 at 10:05:57AM +0000, Mark Marshall wrote:
>>>>>> On 03/03/10 04:19, Keith Hui wrote:
>>>>>> The first problem is that this motherboard only has three DIMM
>>>>>> slots. This means you have to set SDRAMC to something different;
>>>>>> 0x0103 works for me.
>>>>> Hm, seems to be determined by SDRAMPWR + MMCONFIG, and MMCONFIG
>>>>> seems to
>>>>> be a hardware-strap (so we can check it), but not sure about SDRAMPWR.
>>> I think a simple SPD probe would work, if the correct value is returned
>>> you know you have memory in that slot, otherwise if 0xff is returned
>>> then no memory is present. Do this probe for as many slots as the 440
>>> supports. Then set your registers based on that.
>> The issue here is the number of DIMM slots on the motherboard, not the
>> number of sticks in the slots. Some 440BX boards have four slots, while
>> others only have three.
> That is fine. Then if 440bx datasheet says it supports 4 slots, then
> that should be the standard.
Please check this section of the 440BX data sheet.
3.3.24 SDRAMC—SDRAM Control Register (Device 0)
We are interested in bit 4.
SDRAMPWR. The SDRAMPWR bit controls how the CKE signals are driven
for different DRAM configurations. For a 3 DIMM configuration,
SDRAMPWR should be set to ‘0’. For a 4 DIMM configuration,
SDRAMPWR should be set to ‘1’. In this case the 82443BX drives a
single CKE signal (GCKE). The combination of SDRAMPWR and MMCONFIG
(DRAMC register) determine the functioning of the CKE signals.
Refer to the DRAMC register (Section 3.3.15, “DRAMC—DRAM
Control Register (Device 0)” on page 3-19) for more details.
Note: When PCIRST# assertion occurs during POS/STR, these bits
are not reset to 0.
As far as I can tell we cannot auto-detect this. Some (many)
440BX boards only have three DIMM slots, and in these cases the
clocks are routed differently to the boards with four DIMM slots.
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