[coreboot] remove some warning of sb600

Jason Wang wangqingpei at gmail.com
Mon Mar 22 13:20:40 CET 2010


Index: src/southbridge/amd/rs690/rs690_early_setup.c
===================================================================
--- src/southbridge/amd/rs690/rs690_early_setup.c    (revision 5266)
+++ src/southbridge/amd/rs690/rs690_early_setup.c    (working copy)
@@ -128,7 +128,7 @@
 /*
 * Compliant with CIM_33's ATINB_PrepareInit
 */
-static void get_cpu_rev()
+static void get_cpu_rev(void)
 {
     u32 eax, ebx, ecx, edx;
     __asm__ volatile ("cpuid":"=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
@@ -171,7 +171,7 @@
 * Compliant with CIM_33's ATINB_HTInit
 * Init HT link speed/width for rs690 -- k8 link
 *****************************************/
-static void rs690_htinit()
+static void rs690_htinit(void)
 {
     /*
      * About HT, it has been done in enumerate_ht_chain().
@@ -229,7 +229,7 @@
 *    Function2: DRAM and HT technology Trace mode configuration
 *    Function3: Miscellaneous configuration
 *******************************************************/
-static void k8_optimization()
+static void k8_optimization(void)
 {
     device_t k8_f0, k8_f2, k8_f3;
     msr_t msr;
@@ -443,7 +443,7 @@
 }

 /* enable CFG access to Dev8, which is the SB P2P Bridge */
-static void enable_rs690_dev8()
+static void enable_rs690_dev8(void)
 {
     set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
 }
@@ -453,14 +453,14 @@
 /*
 * Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit).
 */
-static void rs690_before_pci_init()
+static void rs690_before_pci_init(void)
 {
 }

 /*
 * The calling sequence is same as CIM.
 */
-static void rs690_early_setup()
+static void rs690_early_setup(void)
 {
     device_t nb_dev = PCI_DEV(0, 0, 0);
     printk(BIOS_INFO, "rs690_early_setup()\n");
Index: src/southbridge/amd/sb600/sb600_smbus.h
===================================================================
--- src/southbridge/amd/sb600/sb600_smbus.h    (revision 5267)
+++ src/southbridge/amd/sb600/sb600_smbus.h    (working copy)
@@ -58,5 +58,7 @@
 #define axindxp_reg(reg, mask, val)    \
     alink_ax_indx(1, (reg), (mask), (val))

+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8
val);

 #endif


-- 
Wang Qing Pei
MSN:wangqingpei at hotmail.com <MSN%3Awangqingpei at hotmail.com>
Gmail:wangqingpei at gmail.com <Gmail%3Awangqingpei at gmail.com>
Phone:86+13426369984
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