[coreboot] [commit] r5306 - in trunk/src/southbridge: amd/cs5530 intel/i82371eb intel/i82801ax intel/i82801bx intel/i82801cx intel/i82801dx intel/i82801gx
repository service
svn at coreboot.org
Sun Mar 28 17:11:56 CEST 2010
Author: stepan
Date: Sun Mar 28 17:11:56 2010
New Revision: 5306
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5306
Log:
drop __ROMCC__ define checks.. __PRE_RAM__ is what the code should be looking for.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Modified:
trunk/src/southbridge/amd/cs5530/cs5530.h
trunk/src/southbridge/intel/i82371eb/i82371eb.h
trunk/src/southbridge/intel/i82801ax/i82801ax.h
trunk/src/southbridge/intel/i82801bx/i82801bx.h
trunk/src/southbridge/intel/i82801cx/i82801cx.h
trunk/src/southbridge/intel/i82801dx/i82801dx.h
trunk/src/southbridge/intel/i82801gx/i82801gx.h
Modified: trunk/src/southbridge/amd/cs5530/cs5530.h
==============================================================================
--- trunk/src/southbridge/amd/cs5530/cs5530.h Sat Mar 27 18:36:39 2010 (r5305)
+++ trunk/src/southbridge/amd/cs5530/cs5530.h Sun Mar 28 17:11:56 2010 (r5306)
@@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_AMD_CS5530_CS5530_H
#define SOUTHBRIDGE_AMD_CS5530_CS5530_H
-#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
+#if !defined(__PRE_RAM__)
#include "chip.h"
void cs5530_enable(device_t dev);
#endif
Modified: trunk/src/southbridge/intel/i82371eb/i82371eb.h
==============================================================================
--- trunk/src/southbridge/intel/i82371eb/i82371eb.h Sat Mar 27 18:36:39 2010 (r5305)
+++ trunk/src/southbridge/intel/i82371eb/i82371eb.h Sun Mar 28 17:11:56 2010 (r5306)
@@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
-#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
+#if !defined(__PRE_RAM__)
#include "chip.h"
void i82371eb_enable(device_t dev);
void i82371eb_hard_reset(void);
Modified: trunk/src/southbridge/intel/i82801ax/i82801ax.h
==============================================================================
--- trunk/src/southbridge/intel/i82801ax/i82801ax.h Sat Mar 27 18:36:39 2010 (r5305)
+++ trunk/src/southbridge/intel/i82801ax/i82801ax.h Sun Mar 28 17:11:56 2010 (r5306)
@@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H
#define SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H
-#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
+#if !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801ax_enable(device_t dev);
#endif
Modified: trunk/src/southbridge/intel/i82801bx/i82801bx.h
==============================================================================
--- trunk/src/southbridge/intel/i82801bx/i82801bx.h Sat Mar 27 18:36:39 2010 (r5305)
+++ trunk/src/southbridge/intel/i82801bx/i82801bx.h Sun Mar 28 17:11:56 2010 (r5306)
@@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H
#define SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H
-#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
+#if !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801bx_enable(device_t dev);
#endif
Modified: trunk/src/southbridge/intel/i82801cx/i82801cx.h
==============================================================================
--- trunk/src/southbridge/intel/i82801cx/i82801cx.h Sat Mar 27 18:36:39 2010 (r5305)
+++ trunk/src/southbridge/intel/i82801cx/i82801cx.h Sun Mar 28 17:11:56 2010 (r5306)
@@ -1,7 +1,7 @@
#ifndef I82801CX_H
#define I82801CX_H
-#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
+#if !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801cx_enable(device_t dev);
#endif
Modified: trunk/src/southbridge/intel/i82801dx/i82801dx.h
==============================================================================
--- trunk/src/southbridge/intel/i82801dx/i82801dx.h Sat Mar 27 18:36:39 2010 (r5305)
+++ trunk/src/southbridge/intel/i82801dx/i82801dx.h Sun Mar 28 17:11:56 2010 (r5306)
@@ -31,7 +31,7 @@
#ifndef I82801DX_H
#define I82801DX_H
-#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
+#if !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801dx_enable(device_t dev);
#endif
Modified: trunk/src/southbridge/intel/i82801gx/i82801gx.h
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/i82801gx.h Sat Mar 27 18:36:39 2010 (r5305)
+++ trunk/src/southbridge/intel/i82801gx/i82801gx.h Sun Mar 28 17:11:56 2010 (r5306)
@@ -39,10 +39,7 @@
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
-/* __ROMCC__ is set by romstage.c to make sure
- * none of the stage2 data structures are included.
- */
-#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
+#if !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801gx_enable(device_t dev);
#endif
More information about the coreboot
mailing list