[coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this

[Idwer Vollering]

2010/5/14 Keith Hui <buurin at gmail.com>

> The original patch was unclean as pork (didn't apply cleanly). Please
> use this one instead.
>
> Thanks Joseph.
>
> And edit your board's romstage similar to patch below:
>
> Index: src/mainboard/asus/p2b-ls/romstage.c
> ===================================================================
> --- src/mainboard/asus/p2b-ls/romstage.c        (revision 5543)
> +++ src/mainboard/asus/p2b-ls/romstage.c        (working copy)
> @@ -33,7 +33,9 @@
>  #include "lib/debug.c"
>  #include "pc80/udelay_io.c"
>  #include "lib/delay.c"
> +#if CONFIG_ROMCC==1
>  #include "cpu/x86/mtrr/earlymtrr.c"
> +#endif
>  #include "cpu/x86/bist.h"
>  /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
>  #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
> @@ -46,12 +48,20 @@
>  }
>
>  #include "northbridge/intel/i440bx/raminit.c"
> +#if CONFIG_DEBUG_RAM_SETUP
>  #include "northbridge/intel/i440bx/debug.c"
> +#endif
>
> -static void main(unsigned long bist)
> +#if CONFIG_ROMCC
> +static /* This is part of main() declaration below for romcc only. */
> +#endif
> +
> +void main(unsigned long bist)
>  {
> +#if CONFIG_ROMCC
>        if (bist == 0)
>                early_mtrr_init();
> +#endif
>
>        /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
>        w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
> @@ -63,10 +73,14 @@
>        i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
>
>        enable_smbus();
> -       /* dump_spd_registers(); */
> +#if CONFIG_DEBUG_RAM_SETUP
> +       dump_spd_registers();
> +#endif
>        sdram_set_registers();
>        sdram_set_spd_registers();
>        sdram_enable();
> -       /* ram_check(0, 640 * 1024); */
> +#if CONFIG_DEBUG_RAM_SETUP
> +       ram_check(0, 640 * 1024);
> +#endif
>  }
>
>
The only additional adjustment I had to make was in raminit.c:

Index: src/northbridge/intel/i440bx/raminit.c
===================================================================
--- src/northbridge/intel/i440bx/raminit.c      (revision 5543)
+++ src/northbridge/intel/i440bx/raminit.c      (working copy)
@@ -947,7 +947,7 @@
        set_dram_row_attributes();

        /* TODO: Set SDRAMC. */
-       pci_write_config16(NB, SDRAMC, 0x0010); /* SDRAMPWR=1: 4 DIMM config
*/
+       pci_write_config16(NB, SDRAMC, 0x0000); /* SDRAMPWR=0: 3 DIMM config
*/

        /* TODO */
        set_dram_buffer_strength();


> >
> > This patch:
> > 1. Brings back L2 initialization from coreboot v1 for family 63x,65x
> > and 67x CPUs. Need someone with a Mendocino Celeron to see if the
> > entire 128k of L2 is still enabled.
> > 2. Split model_67x/65x and model_63x from model_6xx. model_67x also
> > serves model 65x because they share too much code. Also included are
> > Intel microcode for all CPUs in these families. There's just one file
> > for all microcodes in one family.
> > 3. In Slot 1 Makefile.inc, conditionally bring in sources in models
> > 63x/67x/6bx only when the proper config has been selected in Kconfig.
> > Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has
> > been selected.
> > 4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the
> > mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above.
> > 5. Blocked out some apparently unused #includes from model_6xx_init.c.
> > Once we're sure nothing really are using it, then remove them.
> >
> > Bootlog with a PIII 600MHz can be found here:
> > http://coreboot.pastebin.com/PNUzJXZT
>


Bootlog with a 450MHz P3: http://coreboot.pastebin.com/DAqztY9H

[    0.005829] CPU: L1 I cache: 16K, L1 D cache: 16K
[    0.005952] CPU: L2 cache: 512K



> >
> > Have fun, bon appetit and cheers.
> >
>
> Signed-off-by: Keith Hui <buurin at gmail.com>
>
> --
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> http://www.coreboot.org/mailman/listinfo/coreboot
>
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