[coreboot] [RFC] Network console for coreboot

[Rudolf Marek]

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Hello all,

Maybe this story should be for coreboot blog ;)

I have a very short serial cable and therefore I had to always connect the
coreboot machine to the notebook which is bit annoying if I use my workstation
for development.

You may ask how send packets if we have no RAM? Good question so far I know two
answers:

1) use some card with internal SRAM

I know only one... RTL 8029AS which is a NE 2000 compatible PCI card. It has
like 16kb SRAM which is only accessible through PIO.

2) Use some other PCI card with a memory space for packet descriptors, maybe the
sideport memory could work - this is just an idea not tested

Rest was relatively simple. I took the PCI NE2000 driver from gpxe sources, made
it bit more simple (b.c) all routines takes as an argument the IO address of the
card.

How it works:

1) before uart init call net_init() which just setup the BAR0 on card to IOport
0xe00 enable the IO decoding of the card

2) in uart_tx_byte write the byte to card SRAM

3) after the print is done, construct the packet, with fixed MAC and fixed IP,
variable length. The IP payload is UDP packet (src port 6667 dest 6666) The UDP
payload is our text which is already there. Thefore invoke the transmit jut to
transmit it ;)

4) If the PCI slot with the card is bellow some bridge, then situation does
not differ too much. In my case, the first part of the boot is the card on BUS0
but later the PCI slot bus is moved to separate bus (chipset has some bit for
this). Because the bridge has subtractive decoding, the output still works
regardless of the IO forwarding range. The only problem is if coreboot wants to
write new address to BAR0. I solved that by simple hack - I did small PCI driver
which just tells coreboot  the card has fixed and assigned IO resource.

Here is how it looks in linux:

00:13.1 PCI bridge: VIA Technologies, Inc. VT8237A PCI to PCI Bridge (prog-if 01
[Subtractive decode])
	Bus: primary=00, secondary=05, subordinate=05, sec-latency=0
	I/O behind bridge: 00001000-00001fff
	Memory behind bridge: f1200000-f12fffff


05:06.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8029(AS)
	Flags: medium devsel, IRQ 16
	I/O ports at 0e00 [size=32]
	Kernel driver in use: ne2k-pci
	Kernel modules: ne2k-pci

And here how it looks if I catch the output with netcat:

$nc -u -l -p 6666

TEST

coreboot-4.0-r5577M Sun May 30 20:21:52 CEST 2010 starting...
now booting...



INIT detected from  --- { APICID = 00 NODEID = 00 COREID = 00} ---

Issuing SOFT_RESET...
soft reset
TEST

coreboot-4.0-r5577M Sun May 30 20:21:52 CEST 2010 starting...
now booting...
Enabling routing table for node 00 done.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done

<---- snip ---->

Post relocation: addr: 0x00000000000eca00 memsz: 0x0000000000013600 filesz:
0x0000000000009a8e
using LZMA
[ 0x00000000000eca00, 0000000000100000, 0x0000000000100000) <- 00000000fff97c70
dest 000eca00, end 00100000, bouncebuffer 1def0000
Loaded segments
Jumping to boot code at fdfae
entry    = 0x000fdfae
lb_start = 0x00100000
lb_size  = 0x00080000
adjust   = 0x1de70000
buffer   = 0x1def0000
     elf_boot_notes = 0x00118ab0
adjusted_boot_notes = 0x1df88ab0


It goes allright through the boot. Now some questions:

5) The b.c file is from GPXE project and this particular file is under two
Clause BSD license which is compatible with GPL. Can we include this or some
other rewrite needs to be done?

6) SMP? I think we will need some locking ?

7) In case you are wondering where to get RTL8029AS pci card. I asked one big
czech ISP and they found like 20 of this cards. If some of coreboot developers
wants some I can mail it to you with a price of the mail and paypal fee.

8) Someone has free time to fix this patch to something more pretty?


Thanks,
Rudolf
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