[coreboot] [commit] r6123 - in trunk/src: mainboard/gigabyte/m57sli mainboard/msi/ms7260 mainboard/msi/ms9282 mainboard/msi/ms9652_fam10 mainboard/nvidia/l1_2pvv mainboard/supermicro/h8dme mainboard/supermicr...
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svn at coreboot.org
Thu Nov 25 10:03:55 CET 2010
Author: uwe
Date: Thu Nov 25 10:03:55 2010
New Revision: 6123
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6123
Log:
MCP55: Add TINY_BOOTBLOCK support.
Also, move CONFIG_HT_CHAIN_END_UNITID_BASE #ifdef block to mcp55.h to make
the build work (but this is a good idea anyway, as it's used in
multiple files).
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan at coreboot.org>
Added:
trunk/src/southbridge/nvidia/mcp55/bootblock.c
Modified:
trunk/src/mainboard/gigabyte/m57sli/romstage.c
trunk/src/mainboard/msi/ms7260/romstage.c
trunk/src/mainboard/msi/ms9282/romstage.c
trunk/src/mainboard/msi/ms9652_fam10/romstage.c
trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
trunk/src/mainboard/supermicro/h8dme/romstage.c
trunk/src/mainboard/supermicro/h8dmr/romstage.c
trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
trunk/src/mainboard/tyan/s2912/romstage.c
trunk/src/mainboard/tyan/s2912_fam10/romstage.c
trunk/src/southbridge/nvidia/mcp55/Kconfig
trunk/src/southbridge/nvidia/mcp55/chip.h
trunk/src/southbridge/nvidia/mcp55/mcp55.h
trunk/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/romstage.c Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Thu Nov 25 10:03:55 2010 (r6123)
@@ -81,7 +81,6 @@
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@@ -124,7 +123,6 @@
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
- mcp55_enable_rom();
}
if (bist == 0)
Modified: trunk/src/mainboard/msi/ms7260/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/romstage.c Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/mainboard/msi/ms7260/romstage.c Thu Nov 25 10:03:55 2010 (r6123)
@@ -83,7 +83,6 @@
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@@ -125,7 +124,6 @@
/* Allow the HT devices to be found. */
enumerate_ht_chain();
sio_setup();
- mcp55_enable_rom();
}
if (bist == 0)
Modified: trunk/src/mainboard/msi/ms9282/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/romstage.c Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/mainboard/msi/ms9282/romstage.c Thu Nov 25 10:03:55 2010 (r6123)
@@ -96,7 +96,6 @@
#include "cpu/amd/model_fxx/init_cpus.c"
// Disabled until it's actually used:
// #include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@@ -138,7 +137,6 @@
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
- mcp55_enable_rom();
}
if (bist == 0) {
Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Thu Nov 25 10:03:55 2010 (r6123)
@@ -78,7 +78,6 @@
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void)
@@ -117,7 +116,6 @@
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sio_setup();
- mcp55_enable_rom();
}
post_code(0x30);
Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Thu Nov 25 10:03:55 2010 (r6123)
@@ -82,7 +82,6 @@
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@@ -124,7 +123,6 @@
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
- mcp55_enable_rom();
}
if (bist == 0)
Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/romstage.c Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/mainboard/supermicro/h8dme/romstage.c Thu Nov 25 10:03:55 2010 (r6123)
@@ -131,7 +131,6 @@
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@@ -189,7 +188,6 @@
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
- mcp55_enable_rom();
}
if (bist == 0)
Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/romstage.c Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Thu Nov 25 10:03:55 2010 (r6123)
@@ -72,7 +72,6 @@
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@@ -118,7 +117,6 @@
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
- mcp55_enable_rom();
}
if (bist == 0)
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Thu Nov 25 10:03:55 2010 (r6123)
@@ -69,7 +69,6 @@
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void)
@@ -117,7 +116,6 @@
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sio_setup();
- mcp55_enable_rom();
}
post_code(0x30);
Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Thu Nov 25 10:03:55 2010 (r6123)
@@ -75,7 +75,6 @@
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void)
@@ -168,7 +167,6 @@
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sio_setup();
- mcp55_enable_rom();
}
post_code(0x30);
Modified: trunk/src/mainboard/tyan/s2912/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/romstage.c Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/mainboard/tyan/s2912/romstage.c Thu Nov 25 10:03:55 2010 (r6123)
@@ -82,7 +82,6 @@
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@@ -125,7 +124,6 @@
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
- mcp55_enable_rom();
}
if (bist == 0)
Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Thu Nov 25 10:03:55 2010 (r6123)
@@ -79,7 +79,6 @@
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void)
@@ -123,7 +122,6 @@
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sio_setup();
- mcp55_enable_rom();
}
post_code(0x30);
Modified: trunk/src/southbridge/nvidia/mcp55/Kconfig
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/Kconfig Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/southbridge/nvidia/mcp55/Kconfig Thu Nov 25 10:03:55 2010 (r6123)
@@ -2,9 +2,14 @@
bool
select HAVE_USBDEBUG
select IOAPIC
+ select TINY_BOOTBLOCK
if SOUTHBRIDGE_NVIDIA_MCP55
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+ string
+ default "southbridge/nvidia/mcp55/bootblock.c"
+
config ID_SECTION_OFFSET
hex
default 0x80
Added: trunk/src/southbridge/nvidia/mcp55/bootblock.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ trunk/src/southbridge/nvidia/mcp55/bootblock.c Thu Nov 25 10:03:55 2010 (r6123)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
+
+static void bootblock_southbridge_init(void)
+{
+ mcp55_enable_rom();
+}
Modified: trunk/src/southbridge/nvidia/mcp55/chip.h
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/chip.h Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/southbridge/nvidia/mcp55/chip.h Thu Nov 25 10:03:55 2010 (r6123)
@@ -22,6 +22,8 @@
#ifndef MCP55_CHIP_H
#define MCP55_CHIP_H
+#include <device/device.h>
+
struct southbridge_nvidia_mcp55_config
{
unsigned int ide0_enable : 1;
Modified: trunk/src/southbridge/nvidia/mcp55/mcp55.h
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55.h Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55.h Thu Nov 25 10:03:55 2010 (r6123)
@@ -22,13 +22,21 @@
#ifndef MCP55_H
#define MCP55_H
-#include "chip.h"
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
+ #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
+#else
+ #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
+#endif
#ifndef __PRE_RAM__
+#include "chip.h"
void mcp55_enable(device_t dev);
extern struct pci_operations mcp55_pci_ops;
#else
+#if !defined(__ROMCC__)
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-#endif
void mcp55_enable_usbdebug(unsigned int port);
+#endif
+#endif
+
#endif /* MCP55_H */
Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c Thu Nov 25 10:03:55 2010 (r6123)
@@ -21,11 +21,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
- #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
-#else
- #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
-#endif
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include "mcp55.h"
static void mcp55_enable_rom(void)
{
Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c Wed Nov 24 21:03:09 2010 (r6122)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c Thu Nov 25 10:03:55 2010 (r6123)
@@ -28,12 +28,6 @@
#include <device/pci_def.h>
#include "mcp55.h"
-#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
-#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
-#else
-#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
-#endif
-
void set_debug_port(unsigned int port)
{
u32 dword;
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